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| F4PGASlackBridge | <kgugala> @me1 it should be working now | 08:06 |
|---|---|---|
| kgugala | yep, it is | 08:07 |
| F4PGASlackBridge | <acomodi> Yeah, nextpnr is able to handle the Interchange, and from it RapidWright can generate the dcp and open it in the Vivado viewer. There are a set of tests up until a LiteX design capable of running Linux that you can find here: https://github.com/chipsalliance/fpga-interchange-tests | 09:11 |
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| lambda | so uh, nextpnr-xilinx is somehow reversing two pins on my Arty A7 board - U12 and V12 should be PMOD JC[0] and JC[1], respectively, but they're connected to JC[1] and JC[2] | 18:53 |
| lambda | all other PMOD pins are fine | 18:54 |
| lambda | the prjxray-db definitions match up at least with digilent's schematics (U12 is IO_L20P_T3_A08_D24_14, V12 is IO_L20N_T3_A07_D23_14) | 18:56 |
| lambda | oh, my first message should read "they're connected to JC[1] and JC[0]", sorry | 18:56 |
| lambda | I can't find anything about this issue on google, so I doubt it's a board layout issue | 19:02 |
| lambda | ah. https://github.com/gatecat/nextpnr-xilinx/issues/42 | 19:07 |
| lambda | extremely weird that it's only one specific pin pair | 19:07 |
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