Sunday, 2022-11-06

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J0hnHHello, I recently tried out the toolchain with a design that has to run at 100MHz.00:58
J0hnHI got it to work, but getting used to the timing reports is fairly difficult00:59
J0hnHI was wondering if someone has a utility to resolve the $auto and $techmap entries into their signal names01:00
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F4PGASlackBridge<kgugala> @scientes - the buses going into the the FPGA are simply memory mapped. To access from the CPU you just need to read/write correct address. If you're using a system with virtual memory (like e.g. Linux) on the Zynq's CPU, you need to add correct mapping21:12
F4PGASlackBridge<kgugala> check https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM (chapter 4) for Zynq's memory map21:12
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