| F4PGASlackBridge | <hansfbaier> @tmichalak Also, for some reason, the 071-ppips fuzzer does not generate these pseudo pips: https://github.com/kintex-chatter/db-workspace-for-kintex7/commit/5718815414345ba39a91c3f1613184abfd6c5606 What would that mean? | 00:42 |
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| F4PGASlackBridge | <hansfbaier> | 01:08 |
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| F4PGASlackBridge | <hansfbaier> I think the issue is that currently (slightly refactored) the code looks like this: | 01:46 |
| F4PGASlackBridge | <hansfbaier> | 01:47 |
| F4PGASlackBridge | <hansfbaier> So an always statement is only printed if $uphill_pips is a scalar (ie only contains one element). I am not sure if that is intended like that. | 01:47 |
| F4PGASlackBridge | <hansfbaier> Bit RIOI_O0 has two uphill pips: ```==============> PIP: RIOI_X43Y97/RIOI.RIOI_ODELAY0_DATAOUT->RIOI_O0 ====> NODES: RIOI_X43Y97/RIOI_O0 ====> UPHILL PIPS: RIOI_X43Y97/RIOI.RIOI_ODELAY0_DATAOUT->RIOI_O0 RIOI_X43Y97/RIOI.RIOI_OLOGIC0_OQ->>RIOI_O0 dst_wire: RIOI_X43Y97/RIOI_O0 RIOI.RIOI_O0.RIOI_ODELAY0_DATAOUT always ==============> PIP: RIOI_X43Y97/RIOI.RIOI_OLOGIC0_OQ->>RIOI_O0 ====> NODES: RIOI_X43Y97/RIOI_O0 | 01:53 |
| F4PGASlackBridge | ====> UPHILL PIPS: RIOI_X43Y97/RIOI.RIOI_ODELAY0_DATAOUT->RIOI_O0 RIOI_X43Y97/RIOI.RIOI_OLOGIC0_OQ->>RIOI_O0 dst_wire: RIOI_X43Y97/RIOI_O0 RIOI.RIOI_O0.RIOI_OLOGIC0_OQ always``` | 01:53 |
| F4PGASlackBridge | <hansfbaier> So it looks, both RIOI_OLOGIC0_OQ and ODELAY0_DATAOUT are connected to RIOIO_O0 | 02:01 |
| F4PGASlackBridge | <hansfbaier> So according to the prjxray documentation: "The tag `hint` is used for PIPs that are used by Vivado to tell the router that two logic slice outputs drive the same value, i.e., behave like they are connected as far as the routing process is concerned." those two wires should be output as `hint` | 02:03 |
| F4PGASlackBridge | <hansfbaier> Like this: | 02:12 |
| F4PGASlackBridge | <hansfbaier> This will generate a lot of hints in the *IOI* ppips databases though for the other architectures as well | 02:14 |
| F4PGASlackBridge | <hansfbaier> @tmichalak I have created a PR for this: https://github.com/f4pga/prjxray/pull/2063 | 02:23 |
| F4PGASlackBridge | <hansfbaier> Hmm, the problem with this is that it also generates hints for PIPs that are connected to a switch box, like RIOI_X43Y97/RIOI_OLOGIC0_CLKDIVF in the diff above: | 02:27 |
| F4PGASlackBridge | <hansfbaier> So those don't seem to be pseudo pips at all. | 02:29 |
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| F4PGASlackBridge | <tmichalak> Yeah, I think what you showed above confirms that the connection between both RIOI_OLOGIC0_OQ and ODELAY0_DATAOUT and RIOIO_O0 is an always PPIP. So this would rather indicate we should fix the tcl script to take the multiple uphill pips into account and generate both entries with "always" for all of them. nextpnr-xilinx should not avoid printing those since we can see that these connections exist. | 12:01 |
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