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| F4PGASlackBridge | <hansfbaier> I wonder why we got the wrong tile type here in tilegrid.json: | 02:11 |
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| mithro | @kgugala - https://github.com/hdl/conda-eda/pull/272#issuecomment-1371216710 | 17:37 |
| mithro | Also https://github.com/chipsalliance/yosys-f4pga-plugins/issues/432 | 17:48 |
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| JakeZ12 | Hello- his is my first time in irc and my first attempt at using open source fpga tools. Is this a place where I can ask for feedback on an error message I get when building one of the f4pga example projects to bitstream? | 20:46 |
| F4PGASlackBridge | <kgugala> Hi JakeZ12 | 20:51 |
| F4PGASlackBridge | <kgugala> yes, this is a good place to ask | 20:51 |
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| JakeZ12 | great thank you! | 20:59 |
| JakeZ12 | I went through the F4PGA getting started pages and followed the toolchain installation for "Newcomers" which meant setting the environment variables, downloading the tarballs, setting up and activating the conda environment, etc, and then when I go to synthesize and generate the bitstream for the 'timer' example it seems to go through synthesis and | 20:59 |
| JakeZ12 | then I get an error on step #58. "Executing BLIF backend". | 20:59 |
| JakeZ12 | trying to upload a screenshot but it's having trouble | 21:00 |
| JakeZ12 | Error 1: ~/opt/f4pga/xc7/share/f4pga/arch/xc7a50t_test/arch.timing.xml:-1 Failed to open file | 21:04 |
| JakeZ12 | Traceback (most recent call last): | 21:04 |
| JakeZ12 | File "/home/jake/opt/f4pga/xc7/conda/envs/xc7/bin/symbiflow_pack", line 8, in <module> | 21:04 |
| JakeZ12 | sys.exit(pack()) | 21:04 |
| JakeZ12 | File "/home/jake/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 502, in pack | 21:04 |
| JakeZ12 | p_vpr_run(["--pack"] + extra_args, env=p_vpr_env_from_args("pack")) | 21:04 |
| JakeZ12 | File "/home/jake/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 135, in p_vpr_run | 21:04 |
| JakeZ12 | + args, | 21:04 |
| JakeZ12 | File "/home/jake/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/subprocess.py", line 363, in check_call | 21:04 |
| JakeZ12 | raise CalledProcessError(retcode, cmd) | 21:04 |
| JakeZ12 | here is part of the error message, if anyone can help deciphering what my issue is I would greatly appreciate it. I am on Ubuntu | 21:04 |
| JakeZ12 | the file in question "arch.timing.xml" is in the proper location | 21:08 |
| F4PGASlackBridge | <kgugala> `error on step #58. "Executing BLIF backend".` <-- this is still part of synthesis. Is there any more info around this message? | 21:14 |
| F4PGASlackBridge | <kgugala> you can upload the logs to e.g. pastebin and link here | 21:15 |
| JakeZ12 | https://pastebin.com/sHLa5KVi | 21:16 |
| JakeZ12 | darn, I thought I made it out of the synthesis step '=D | 21:16 |
| F4PGASlackBridge | <kgugala> the log you pasted doesn't have the BLIF error | 21:20 |
| JakeZ12 | https://pastebin.com/bTnUECzZ | 21:22 |
| JakeZ12 | I just left out the line that says "58. Executing BLIF backend" | 21:22 |
| F4PGASlackBridge | <kgugala> ok, so it finished synthesis | 21:22 |
| F4PGASlackBridge | <kgugala> the error is from VPR | 21:22 |
| F4PGASlackBridge | <kgugala> not yosys | 21:22 |
| F4PGASlackBridge | <kgugala> hmm I just did everything from scratch and it works fine | 21:30 |
| F4PGASlackBridge | <kgugala> I followed https://f4pga-examples.readthedocs.io/en/latest/index.html | 21:30 |
| F4PGASlackBridge | <kgugala> can you try doing a fresh clone and going through the docs command by command? | 21:30 |
| F4PGASlackBridge | <kgugala> the commands from the docs are tested in CI and are "green" | 21:31 |
| F4PGASlackBridge | <kgugala> this is the latest CI run https://github.com/chipsalliance/f4pga-examples/actions/runs/3833944347/jobs/6525865777 | 21:32 |
| F4PGASlackBridge | <kgugala> all ubuntu tests (actually all the tests) are passing | 21:32 |
| JakeZ12 | yeah I'll go through it again step by step and make sure I didn't make any errors along the way. I appreciate your help thank you | 21:34 |
| F4PGASlackBridge | <kgugala> BTW which example you tried to build | 21:35 |
| JakeZ12 | I was trying to build the "timer" example | 21:36 |
| JakeZ12 | cd to f4pga-examples/xc7 and ran make -C timer | 21:37 |
| F4PGASlackBridge | <kgugala> I checked with counter | 21:37 |
| F4PGASlackBridge | <kgugala> let me try timer | 21:37 |
| F4PGASlackBridge | <kgugala> and which target? | 21:37 |
| F4PGASlackBridge | <kgugala> it defaults to BASYS | 21:38 |
| F4PGASlackBridge | <kgugala> seems to be working in my case | 21:39 |
| JakeZ12 | yeah the basys3 board | 21:39 |
| F4PGASlackBridge | <kgugala> I have similar logs as in CI https://github.com/chipsalliance/f4pga-examples/actions/runs/3833944347/jobs/6525866282 | 21:39 |
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