| *** jacobk <jacobk!~quassel@utdpat241106.utdallas.edu> has quit IRC | 02:12 | |
| *** bl0x_ <bl0x_!~bl0x@p54a708b1.dip0.t-ipconnect.de> has joined #f4pga | 02:14 | |
| *** bl0x <bl0x!~bl0x@p200300d7a744ee007eeb7a11c5915eaa.dip0.t-ipconnect.de> has quit IRC | 02:15 | |
| *** jacobk <jacobk!~quassel@64.189.201.150> has joined #f4pga | 02:27 | |
| *** bjorkintosh <bjorkintosh!~bjork@user/bjorkintosh> has quit IRC | 08:45 | |
| *** jacobk <jacobk!~quassel@64.189.201.150> has quit IRC | 12:17 | |
| *** chexum <chexum!~quassel@gateway/tor-sasl/chexum> has quit IRC | 13:35 | |
| *** chexum <chexum!~quassel@gateway/tor-sasl/chexum> has joined #f4pga | 13:35 | |
| *** jacobk <jacobk!~quassel@64.189.201.150> has joined #f4pga | 16:17 | |
| *** TMM_ <TMM_!hp@amanda.tmm.cx> has quit IRC | 16:40 | |
| *** TMM_ <TMM_!hp@amanda.tmm.cx> has joined #f4pga | 16:40 | |
| *** jacobk_ <jacobk_!~quassel@utdpat241106.utdallas.edu> has joined #f4pga | 17:18 | |
| *** jacobk <jacobk!~quassel@64.189.201.150> has quit IRC | 17:20 | |
| *** bjorkintosh <bjorkintosh!~bjork@2600:1700:5400:c80:2c91:14a9:4c3d:68ae> has joined #f4pga | 17:22 | |
| *** bjorkintosh <bjorkintosh!~bjork@user/bjorkintosh> has joined #f4pga | 17:22 | |
| *** jacobk_ is now known as jacobk | 17:24 | |
| *** Nuliel <Nuliel!~Nuliel@176-131-17-174.abo.bbox.fr> has joined #f4pga | 18:23 | |
| *** Nuliel <Nuliel!~Nuliel@176-131-17-174.abo.bbox.fr> has quit IRC | 18:24 | |
| *** Nuliel <Nuliel!~Nuliel@176-131-17-174.abo.bbox.fr> has joined #f4pga | 18:24 | |
| Nuliel | Hello, | 18:35 |
|---|---|---|
| Nuliel | I would like to learn programming fpga, and I would like to avoid the proprietary tools if possible. I've seen many different open-source toolchains for fpga: f4pga, oss-cad-suite-build, amaranth-hdl. What are the differences between all these toolchains? What are the limitations of these toolchains? Do these toolchains use the same tools (I've | 18:35 |
| Nuliel | seen yosys and nextpnr)? | 18:35 |
| Nuliel | I have searched long enough but it continues to remain unclear for me :/ | 18:35 |
| Nuliel | Also, if you have a good ressource to learn VHDL, I'm interested :) | 18:35 |
| *** jacobk <jacobk!~quassel@utdpat241106.utdallas.edu> has quit IRC | 20:45 | |
| jn | Nuliel: amaranth is more of a different programming language that acts as a front-end to the other toolchains | 20:50 |
| Nuliel | thank you for your answer jn, ok for amaranth. And between f4pga and oss-cad-suite-build, what is the difference? | 20:55 |
| jn | Nuliel: as far as i've understood, oss-cad-suite bundles a lot of open source tools (including yosys, nextpnr, trellis/icestorm/etc.); i don't know f4pga well enough to describe it | 21:25 |
| Nuliel | jn: ok, I think I will see to buy a lattice icestick (or another compatible fpga, I need to look for the differences between all of them) and try the two projects | 21:33 |
| jn | for ice40, i think yosys + nextpnr + icestorm is suffient. how you install them is up to you, of course | 21:34 |
| jn | personally, i think amaranth is worth checking out, i quite enjoy using it | 21:34 |
| bl0x_ | +1 for amaranth, but IMO it is very important to also get a good understanding of the basics in either vhdl or verilog. | 21:37 |
| jn | verilog is probably a bit easier to find context for, because yosys supports it natively and amaranth generates it | 21:38 |
| Nuliel | ok, I will also try amaranth. For now, I just successfully blinked a led on a arrow fpga (it was not mine), so yes I need to learn all the basics. | 21:42 |
| Nuliel | ok for verilog. Is there a big difference between verilog and vhdl or it's just a different syntax? | 21:42 |
| *** pbsds <pbsds!~pbsds@193.71.241.70> has quit IRC | 21:42 | |
| *** pbsds <pbsds!~pbsds@193.71.241.70> has joined #f4pga | 21:43 | |
| bl0x_ | For verilog and ice stick I can recommend the tutorial series learnFpga by Bruno Levy. There you'll build a CPU from scratch in verilog. | 21:44 |
| Nuliel | oh cool! I will follow this tutorial with an icestick as this fpga seems to be often used and not too expensive. Thank you for all your answers! | 21:52 |
| bjorkintosh | Nuliel, they have different origins. Syntax-wise, Verilog is more like C (but not quite) and VHDL is more like ADA (but not exactly) | 21:58 |
| Nuliel | ok, so I should be more comfortable with verilog as I code mainly in C | 22:01 |
| Nuliel | (I never coded in ADA) | 22:01 |
| bjorkintosh | most haven't. but it is a good and powerful language. | 22:03 |
| *** chexum <chexum!~quassel@gateway/tor-sasl/chexum> has quit IRC | 22:03 | |
| *** chexum <chexum!~quassel@gateway/tor-sasl/chexum> has joined #f4pga | 22:06 | |
| Nuliel | ok, I will take a look at vhdl also to choose between verilog and vhdl. Thank you! I will go, have a nice evening! | 22:17 |
| *** Nuliel <Nuliel!~Nuliel@176-131-17-174.abo.bbox.fr> has quit IRC | 22:18 | |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!