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| TMM_ | Hi all! I've been trying to reorient myself back towards FPGA design after some fruitless attempts to make the thing I wanted from existing ASICs, mostly due to availability issues. Basically what I'm trying to do is implement a SCSI interface that can implement up to about UW-160 speeds of SCSI commands. I think I have a vague understanding now of what I need to do, but I kind of suspect that my arty a7-35T might not be up to the task. I'm thinking perhaps the ecp5 | 16:04 |
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| TMM_ | might be a good choice? But regardless I'll need some kind of cpu to interface it with. My original plan was to basically just stuff a rocket risc-v core on there for that purpose but then I'll end up having to interface that to some other CPU again to do the high-level emulation that I need. | 16:04 |
| TMM_ | I was wondering if there's any of those ARM+FPGA targets that are supported by F4PGA that I could use, and that in total would result in a fully open source system without any binary blobs anywhere. I find it hard to evaluate these things as the manufacturers don't seem to really bother noting any of those types of details ;) | 16:05 |
| jn | perhaps not completely relevant, but i think https://github.com/lethalbit/squishy can offer some inspiration regarding FPGA + SCSI | 16:09 |
| tnt | I'd say both a A35T and an ECP5 would be just fine to emulate a UW-160. And I don't see why you would need 2 CPUs either. | 16:10 |
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| TMM_ | tnt: there is some user-space stuff like reading from SD cards and maybe proving some kind of display of currently selected images. I figured writing that in C or something on freertos or something along those lines would be easier than trying to do all of that on the fpga. | 17:05 |
| TMM_ | But, I'm really not very experienced with this stuff at all. I'm not trying to argue, just sharing my thought process as an invitation to tell me I'm wrong :P | 17:06 |
| TMM_ | Ahhhhh, I didn't understand that squishy was written in python but generates verilog | 17:10 |
| TMM_ | I guess I could instantiate a rocket-riscv cpu, have the scsi command handling implemented on a freertos thread with high priority and the user interface stuff on low priority | 17:20 |
| TMM_ | I think I really only need the fpga for bus arbitration and timing and interrupt sending, I think most of the scsi protocol I should probably just implement in C or rust or something | 17:21 |
| TMM_ | So, I guess I'd use a rocket risc-v core then, with a custom design for the scsi bus interface, with a wishbone interface to the rocket core, some ram and some flash and some spi busses for sd cards | 17:22 |
| TMM_ | And some external scsi bus transceiver chips | 17:22 |
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