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| TMM_ | Hey all! I wondered if there's any policy on what system verilog features are and aren't supported in Yosys, there's a couple of features I'd like to use that don't exist. I wouldn't mind impementing them in iverilog and yosys so I can use them, but I'd rather not spend a bunch of time trying to implement something only to find out it's not supported on purpose! :) | 12:11 |
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| TMM_ | The workflow I've settled on is basically to use iverilog with it's simulator for most dev/test cycles, with occasionally using yosys to systhensize to ice40 to verilog and then compiling the results with iverilog and simulating that before moving to hardware. So I'll probably be trying to make sure that the feature sets between the two match enough for me to do this | 12:12 |
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