| openpowerbot | [slack] <Benjamin Herrenschmidt> Guys, I "designed" the debug interface a while ago as a quick & dirty thing to get going 🙂 | 13:43 |
|---|---|---|
| openpowerbot | [slack] <Benjamin Herrenschmidt> basic idea is to have an internal debug "bus" that iis super simple in order to not make a mess of the units it connects to | 13:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that said I'm not happy with the design | 13:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it's too slow and can't effectively "stream" stuff from memory | 13:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (or to memory) | 13:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it probably needs to be rejigged a bit | 13:45 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but jtag is always problematic because it's a clock domain boundary | 13:45 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> so probably needs a more "packetized" protocol with a fifo to cross the clock domains | 13:45 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that way one can much much better stream data in/out | 13:45 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but keep in mind I'm not a HW dev so any vhdl I write is basically random shit by a newbie :)) | 13:46 |
| lkcl | Ben: the DMI interface is pretty good, it works really well. | 15:28 |
| lkcl | yes, CDC is standard for JTAG, and "not the DMI's problem". in Libre-SOC, Staf Verhagen's JTAG-TAp interface can even take care of *which* clock-domain you want to sync with, by passing the domain in as an optional argument | 15:29 |
| lkcl | https://gitlab.com/Chips4Makers/c4m-jtag/-/commit/b4aa89548fd7439eda24979ab7d8a516c22a360b#ff65c9cc7230e9bae928a90e16d90cf59e70d375 | 15:30 |
| lkcl | here is for example where you can specify the parameters of a Shift Register that you want created (and to be managed by C4M JTAG TAP) | 15:31 |
| lkcl | https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L516 | 15:31 |
| lkcl | one of the arguments is: ... | 15:32 |
| lkcl | ... the clock domain against which the CDC-synchronisation is to take place | 15:32 |
| lkcl | likewise when adding a Wishbone Interface | 15:32 |
| lkcl | https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L606 | 15:32 |
| lkcl | again, the domain may be specified | 15:33 |
| lkcl | likewise here is where i added DMI Interface support | 15:33 |
| lkcl | https://git.libre-soc.org/?p=c4m-jtag.git;a=commitdiff;h=6b2a90b3dddda411e096e577a9f7b35fe2492878 | 15:33 |
| lkcl | again: the CDC domain may be specified as an optional argument | 15:34 |
| lkcl | and it is the *JTAG TAP* interface that is responsible for the Clock Domain Crossing | 15:34 |
| lkcl | *not* the DMI interface itself | 15:34 |
| lkcl | for random shit by a newbie the DMI module and the interface itself is pretty damn good :) | 15:34 |
| lkcl | two things i would request: | 15:35 |
| lkcl | 1) not to make large changes without synchronising with us, because we critically rely on the DMI registers and functions for interoperability. i.e. it's basically *already* a de-facto standard | 15:35 |
| lkcl | 2) to discuss increasing the size of the DMI "Address" (from 4 to 5 or even 6 bits) because we need to add extra registers. | 15:36 |
| lkcl | three things | 15:36 |
| lkcl | 3) to discuss and standardise the GPR / FPR / SPR / etc registers because we're adding SVP64. | 15:37 |
| lkcl | GPR and FPR are extending to 128. those need to be accessible | 15:37 |
| lkcl | CR Fields are extending to 128 (a total of QTY 16of 32-bit CRs, not QTY 1of 32-bit CRs) | 15:38 |
| lkcl | and PC+MSR "state" is now PC+MSR+SVSTATE, where SVSTATE is a true peer *of* PC and MSR (SVSTATE contains the "Sub-Program-Counter") | 15:38 |
| lkcl | and consequently needs an additional SVSRR0 for interrupt context switching. | 15:39 |
| lkcl | PC <=> SRR0 | 15:39 |
| lkcl | MSR <=> SRR1 | 15:39 |
| lkcl | SVSTATE <=> SVSRR0 | 15:39 |
| lkcl | so there are quite a few practical things | 15:39 |
| lkcl | but the overall principle of DMI is pretty straightforward, pretty sound, and works extremely well. | 15:40 |
| lkcl | for Libre-SOC we added memory read/write btw via the JTAG TAP interface. Staf of Chips4Makers has already added a Wishbone Bus accesser. | 15:42 |
| lkcl | it's very well designed. | 15:42 |
| lkcl | https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L656 | 15:43 |
| lkcl | it is state-based. | 15:43 |
| lkcl | the FSM involves auto-incrementing of the address. | 15:44 |
| lkcl | so, like DMI GPR/registers, there is a DMI command for setting "the register you want to read/write" | 15:45 |
| lkcl | and another DMI command "to get the contents of where the DMI-reg-addr command pointed to" | 15:45 |
| lkcl | exactly the same thing is done in Staf's C4M-JTAG TAP module... | 15:46 |
| lkcl | except that after each read/write "to get the actual contents of the register (memory address)", the register (memory address) is *auto-incremented* | 15:46 |
| lkcl | so you can do: | 15:46 |
| lkcl | * one command to set which register (memory address) you want to start reading from | 15:47 |
| lkcl | * multiple sequential commands to just read register contents | 15:47 |
| lkcl | no need to do | 15:47 |
| lkcl | command to set address | 15:47 |
| lkcl | command to get data | 15:47 |
| lkcl | command to set address | 15:47 |
| lkcl | command to get data | 15:47 |
| lkcl | ... | 15:47 |
| lkcl | ... | 15:47 |
| lkcl | that would be a valuable improvement i could get behind, as long as it's backwards-compatible with the (laborious, non-optimised) case. which should be pretty easy to ensure | 15:48 |
| lkcl | hmmm, only thing being, if people assume, "oh, i can read multiple times, it will get the contents of the exact same register", it's probably a good idea to have a *new* DMI command | 15:49 |
| lkcl | "read-register-and-auto-increment-the-GPR-address" | 15:49 |
| lkcl | toshywoshy: again, all of these things are exactly the kinds of things that should be discussed and agreed by a Formal Debug ISA WG | 15:50 |
| lkcl | (with appropriate "open" governance and "open" contributions i.e. not locked behind secret membership, because, as you know, participation in that would be a conflict of interest with our funding body, NLnet) | 15:51 |
| lkcl | s/that/of that type/ | 15:52 |
| lkcl | i can kiinda see a case for adding memory-access to DMI? although.... yep | 16:19 |
| lkcl | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf | 16:19 |
| lkcl | it's part of the RISKV Debug Specification | 16:19 |
| lkcl | which is much more complete and sophisticated. includes selecting which core is to be queried. | 16:21 |
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