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| openpowerbot | [slack] <Benjamin Herrenschmidt> I just find it hard to get my head around those kind of HDL-generator language | 13:23 |
|---|---|---|
| openpowerbot | [slack] <Benjamin Herrenschmidt> for some obscure reason, despite having mostly a SW background, I find that I reason better with a "pure" HDL like verilog of vhdl | 13:24 |
| * openpowerbot [mattermost] <lkcl> waves hello to henriok | 16:54 | |
| openpowerbot | [mattermost] <lkcl> Ben: i hear ya. VHDL is, fascinatingly, based on Ada, and is near gate-level in its concepts. no coincidence that A2I chose it for high-performance and expression of all ALUs in barely-above-gate-level form | 16:55 |
| openpowerbot | [mattermost] <lkcl> likewise as a software engineer, i found that nmigen was almost impossible to relate to gate-level, and for about 5 months i had to use yosys "read_ilang file.il; show top" on every single modification. | 16:56 |
| openpowerbot | [mattermost] <lkcl> the same trick can be deployed with verilog ("read_verilog") | 16:56 |
| openpowerbot | [mattermost] <lkcl> but for microwatt you'd have to go through a bit of hassle, jump through some hoops (compile with ghdl first then use yosys-ghdl-plugin to "extract" the netlist), before being able to show it | 16:57 |
| openpowerbot | [mattermost] <lkcl> then at the gate level, it's all the same :) | 16:57 |
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