| openpowerbot | [slack] <Paul Mackerras> <@UNG0KE3B7> this trace shows why we get garbage on the serial port initially : https://files.slack.com/files-pri/T443QD9JA-F02HT98R1U5/download/tek0000.jpg | 06:50 |
|---|---|---|
| openpowerbot | [slack] <Paul Mackerras> the top trace is the serial port transmit line, the middle trace is system_clk divided by 4000, the bottom trace is system_clk_locked | 06:51 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> What is what here ? | 06:51 |
| openpowerbot | [slack] <Paul Mackerras> the first char out takes ~130us vs. about 87us which it should take | 06:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Oh the clock is ramping slowly up to speed ? | 06:52 |
| openpowerbot | [slack] <Paul Mackerras> looks like it | 06:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Odd | 06:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Too much load on one clock line ? | 06:52 |
| openpowerbot | [slack] <Paul Mackerras> how would that affect the frequency? | 06:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I think I only see that after config via that, not when loading from flash | 06:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Dunno .. analog magic in pill ? :-) | 06:53 |
| openpowerbot | [slack] <Paul Mackerras> this is when loading from flash on the orange crab (lattice ecp5) | 06:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Ugh so not Xilinx specific | 06:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Very odd | 06:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Could it be voltage drop at startup affecting it ? Are crystal voltage sensitive ? | 06:54 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> We can always put some logic to wait 20000 clocks before releasing reset :/) | 06:55 |
| openpowerbot | [slack] <Matt Johnston> hm. or the PLL lock signal is premature? | 06:55 |
| openpowerbot | [slack] <Paul Mackerras> yes it does seem to be premature | 06:55 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Ask the hw guys, they might know | 06:55 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I don't know. I would assume it's rather different between xilimx and lattice | 06:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> It's funny that we observe the same effect | 06:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Didn't find anything on Google last time I searched | 06:59 |
| openpowerbot | [slack] <Matt Johnston> Paul can you see how long it is between power-on and system_clk_locked? the orangecrab's oscillator is specced as 5ms. https://ele.kyocera.com/assets/products/crystal-device/clock_k_e.pdf | 07:13 |
| openpowerbot | [slack] <Jeremy Kerr> wait, you have "hw guys" for microwatt now? 🙂 | 07:20 |
| openpowerbot | [slack] <Paul Mackerras> This is not power-on, I'm hitting the reset line on the OC | 07:34 |
| openpowerbot | [slack] <Paul Mackerras> which is the PROGRAMN input on the fpga | 07:35 |
| openpowerbot | [slack] <Matt Johnston> oh, right. guess at least if the ext_clk is reliable that can be used as a startup delay... | 07:36 |
| openpowerbot | [slack] <Paul Mackerras> turns out there is no pll locked signal being generated, which is worked around by this hack in fpga/clk_gen_ecp5.vhd: | 08:25 |
| openpowerbot | [slack] <Paul Mackerras> ``` pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!?``` | 08:25 |
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| openpowerbot | [slack] <Benjamin Herrenschmidt> So could be a different issue from xilinx | 10:58 |
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