| lkcl | that would be a great one to have under the new FOSDEM VLSI/FPGA devroom https://libre-soc.org/conferences/fosdem2022/ | 13:12 |
|---|---|---|
| lkcl | paul, mikey et al, i wanted to ask: how the heck does the register file hazard-protection work in microwatt? | 13:13 |
| lkcl | i'm seeing this https://github.com/antonblanchard/microwatt/blob/master/writeback.vhdl | 13:13 |
| lkcl | and it looks like it's creating an exclusive per-pipeline "spinlock", if you will | 13:14 |
| lkcl | it seems that the principle is: only one pipeline (of which it now looks like there are 3) at a time is permitted write-access to regfiles | 13:14 |
| lkcl | although that's not making sense. | 13:16 |
| lkcl | ah ha! is this it? | 13:17 |
| lkcl | common.vhdl | 13:17 |
| lkcl | Decode2ToExecute | 13:17 |
| lkcl | read_data1: std_ulogic_vector(63 downto 0); | 13:17 |
| lkcl | read_data2: std_ulogic_vector(63 downto 0); | 13:17 |
| lkcl | nope, that's the data in (*from* the regfiles), isn't it | 13:18 |
| lkcl | there must _be_ some read-after-write and write-after-read hazard protection, otherwise you get catastrophic data corruption | 13:19 |
| lkcl | i just can't find it! :) | 13:20 |
| lkcl | ahhhh https://github.com/antonblanchard/microwatt/blob/7fa7b45faa17950de44591f7a73722fdf8a87385/control.vhdl#L136 | 13:20 |
| lkcl | ah. pipeline stage length counting :) | 13:22 |
| lkcl | only works for things with guaranteed (fixed) pipeline lengths | 13:23 |
| lkcl | FP and DIV, being FSMs of indeterminate length, would not fit that, nor, strictly, would LD/sT based on stalls from the Wishbone Bus. but everything else, yeah. nice | 13:24 |
| lkcl | sorry. LDs. STs would be fine (ish) but LDs would not. the wishbone bus is not fixed / guaranteed length (outside of the control of the core due to wishbone stall signals) | 13:25 |
| openpowerbot | [mattermost] <lkcl> in Libre-SOC i have a Set-Reset (SR) Latch (okok, actually a DFF register which has some if-statements that prioritise "reset" - set to 0 - over "set" - set to 1) | 15:45 |
| openpowerbot | [mattermost] <lkcl> and that's a bitvector | 15:46 |
| openpowerbot | [mattermost] <lkcl> where decoding of reads (RA, RB, RC, RS aka in1/in2/in3) will set the relevant bit (0..31) | 15:46 |
| openpowerbot | [mattermost] <lkcl> and on write the corresponding bit is cleared | 15:47 |
| openpowerbot | [mattermost] <lkcl> means that the same bitvector hazard protection can cover FSMs such as FP pipeline operations, and DIV, and indeterminate-lengthed-LD operations | 15:47 |
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