Tuesday, 2021-12-14

openpowerbot_[slack] <Jeremy Kerr> hm, any chance we could do a LPC controller under microwatt, as the host-side of a BMC <--> host system?02:25
openpowerbot_[slack] <Jeremy Kerr> would solve some OpenBMC-for-ppc64 hardware availability issues02:25
openpowerbot_[slack] <joel> @jk a lpc host, to go with the lpc peripheral that @Michael Neuling @Anton Blanchard wrote?02:59
openpowerbot_[slack] <Jeremy Kerr> @joel not necessarily - would be handy to connect to an existing BMC too03:56
openpowerbot_[slack] <Jeremy Kerr> (I'm after an easy way to get a ppc64 host system talking LPC to a BMC)03:57
openpowerbot_[slack] <joel> Ah yes, that would be cool to have. I'd be interested in something similar for FSI!07:06
openpowerbot_[slack] <joel> FYI, there's a regression in building with the latest yosys that I hit today. I opened an issue against yosys, any help is appreciated as I'm not quite sure what the issue is: https://github.com/YosysHQ/yosys/issues/310907:10
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openpowerbot_[mattermost] <lkcl> that's bizarre, but quite fundamental / critical: the command has changed and the behaviour has changed.  an extra "pass" is now inserted - Pass::call(design, argv); - passing anything ".v" to "vlog2k" rather than to the prior command "verilog" https://github.com/YosysHQ/yosys/commit/0cbdb42dcd74090296aa3fe6bf11db1c288d996212:01
openpowerbot_[mattermost] <lkcl> so it's probably the case that the behaviour has changed by treating files of type ".v" as a [completely different?] verilog syntax / subset12:02

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