openpowerbot | [mattermost] <lkcl> mmm, just got an interesting bug in dcache, by using a wishbone bus that is fully pipelined | 19:12 |
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openpowerbot | [mattermost] <lkcl> the scenario is: | 19:12 |
openpowerbot | [mattermost] <lkcl> * stb instruction when priv_mode=1 and virt_mode=1 | 19:13 |
openpowerbot | [mattermost] <lkcl> * dcache invalid PTE occurs, triggers MMU RADIX walk | 19:14 |
openpowerbot | [mattermost] <lkcl> * RADIX walk proceeds and fires off a sequence of wishbone *pipelined* lookups | 19:14 |
openpowerbot | [mattermost] <lkcl> * dcache responds with one of the *early* entries of the batch of QTY8 pipelined lookups | 19:15 |
* openpowerbot [mattermost] <lkcl> loadstore is told that the PTE is valid whilst dcache is still in the middle of a batch of 8 lookups | 19:15 | |
openpowerbot | [mattermost] <lkcl> * loadstore requests dcache to continue the stb instruction | 19:16 |
* openpowerbot [mattermost] <lkcl> STORE_REQ_MISS operation is engaged whilst dcache is still in RELOAD_WAIT_ACK state | 19:17 | |
openpowerbot | [mattermost] <lkcl> (mmu_req is still in progress, basically) | 19:18 |
openpowerbot | [mattermost] <lkcl> * STORE request is DROPPED on the floor | 19:20 |
openpowerbot | [mattermost] <lkcl> in the non-pipelined version (wishbone stall = stb & ~ack) it is a pure coincidence, by sheer luck, that the ack inside RELOAD_WAIT_ACK is not enabled, and like two high-speed cars on a figure-8 the two operations miss each other | 19:22 |
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