| openpowerbot | [slack] <Jeremy Kerr> getting some interesting memtest failures | 06:31 |
|---|---|---|
| openpowerbot | [slack] <Jeremy Kerr> ```memtest_data error @ 0x40000000: 0xb320bd03 vs 0x80200003 | 06:31 |
| openpowerbot | [slack] <Jeremy Kerr> memtest_data error @ 0x40000004: 0x80300002 vs 0xc0300002 | 06:31 |
| openpowerbot | [slack] <Jeremy Kerr> memtest_data error @ 0x40000008: 0xc0180001 vs 0x60180001 | 06:31 |
| openpowerbot | [slack] <Jeremy Kerr> memtest_data error @ 0x4000000c: 0x602c0003 vs 0xb02c0003 | 06:31 |
| openpowerbot | [slack] <Jeremy Kerr> memtest_data error @ 0x40000010: 0xb0360002 vs 0xd8360002``` | 06:31 |
| openpowerbot | [slack] <Jeremy Kerr> looks like the odd bytes are one "cycle" behind | 06:31 |
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| openpowerbot | [mattermost] <lkcl> jeremy: intriguing. what's the context? ECP5? Arty-A7? Verilator simulation? is that DRAM (DDR3) or SDRAM1? | 11:37 |
| openpowerbot | [slack] <Matt Johnston> lkcl: orangecrab, so ecp5 with ddr3. running 48mhz, though 55mhz was similar | 11:42 |
| openpowerbot | [mattermost] <lkcl> does it also occur under verilator-simulation? | 12:21 |
| openpowerbot | [mattermost] <lkcl> the reason i ask is for triaging which side of the LD/ST wishbone interface it is (i.e. in microwatt, or in the PHY) | 12:22 |
| openpowerbot | [mattermost] <lkcl> although, i did see things like this when getting the DRAM timing params not quite right | 12:22 |
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