| openpowerbot_ | [slack] <mithro> @joel - Yes we could most certainly ghdl ahd the ghdl yosys plugin added to conda-eda | 02:03 |
|---|---|---|
| openpowerbot_ | [slack] <mithro> @joel - Actually it looks like it might already be done? -> https://github.com/hdl/conda-eda/blob/master/syn/ghdlsynth/build.sh | 02:04 |
| openpowerbot_ | [slack] <mithro> @joel - Actually it looks like it might already be done? -> https://github.com/hdl/conda-eda/blob/master/syn/ghdlsynth/build.sh | 02:04 |
| openpowerbot_ | [slack] <mithro> @joel Can you log a github issue @ https://github.com/hdl/conda-eda/issues -- I'm sure that between Antmicro, Johan / mailto:proppy@google.com and Unai / umarcor we can get it packaged pretty quickly. | 02:06 |
| openpowerbot_ | [mattermost] <lkcl> mithro: and the issues which cause vtr to segfault, and only be capable of supporting microwatt at 25 mhz? | 15:02 |
| openpowerbot_ | [mattermost] <lkcl> the first time that that was reported was several months ago, by someone working on the IBM India sponsored educational course | 15:03 |
| openpowerbot_ | [mattermost] <lkcl> he did not receive a response | 15:03 |
| openpowerbot_ | [mattermost] <lkcl> the second time was me reporting it, a couple of weeks ago | 15:03 |
| openpowerbot_ | [mattermost] <lkcl> i did not receive a response | 15:03 |
| openpowerbot_ | [mattermost] <lkcl> the first time that the segfault was reported was several months ago, by someone working on the IBM India sponsored educational course | 15:04 |
| openpowerbot_ | [mattermost] <lkcl> i have now tracked down how the segfault can be solved | 15:06 |
| openpowerbot_ | [mattermost] <lkcl> i have not received a response | 15:06 |
| openpowerbot_ | [mattermost] <lkcl> Peter: yes, i have seen some, they are quite amusing and understandable workarounds: the CARRY4 "rework" script, which exports to JSON, runs some python to rework the AST, re-imports and carries on. as a hack i quite like it :) but, strictly speaking, long-term, that should be rewritten as a techmap phase in upstream yosys or in the symbiflow_xilinx plugin. | 15:10 |
| openpowerbot_ | [mattermost] <lkcl> the default techmap for xilinx FPGAs creates a long-chain cascade of CARRY4 blocks. there is no attempt at optimisation there *at all* - that's done by the python-based elegant-pragmatic-hack-job-script | 15:11 |
| openpowerbot_ | [mattermost] <lkcl> if you set symbiflow_xilinx "-nocarry" option, that uses LUT4/5/6s *not* the CARRY4 blocks built-in to the A7s - it's the default fall-back techmap for add/sub/cmp - and that *is* optimised | 15:12 |
| openpowerbot_ | [mattermost] <lkcl> it uses (as best i can tell) some form of carry-forward-propagation algorithm. | 15:13 |
| openpowerbot_ | [slack] <mithro> lkcl: If you are unwilling to create a bug report with details, it is unlikely it will get fixed quickly. | 15:51 |
| openpowerbot_ | [mattermost] <lkcl> mithro: please provide the location on OpenPOWER Foundation resources where you would like the bugreport to be submitted. | 18:45 |
| openpowerbot_ | [mattermost] <lkcl> please respect that i have obligations which prevent me from utilising github. | 18:46 |
| openpowerbot_ | [mattermost] <lkcl> you are fully and keenly aware of this already, please do not pretend that you are not | 18:46 |
| openpowerbot_ | [mattermost] <lkcl> it is disingenuous and insulting and i am deeply upset and offended by your assumption that i am "unwilling" to create a bugreport. | 18:47 |
| openpowerbot_ | [slack] <mithro> We each have our own limitations, resources and priorities. I understand that you have decided to work with restrictions that might mean it is impossible for you to report the bug and collaborate with other teams. The SymbiFlow, Yosys, Microwatt and Verilog to Routing projects all use GitHub for tracking bugs which they use to figure out how to prioritize what to work on. Without getting something logged the | 20:15 |
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