| openpowerbot | [mattermost] <lkcl> sigh this is getting quite irritating for me. closer inspection of the gtkwave traces shows a corner-case that *nmigen-soc* cannot handle: it looks like microwatt dcache.vhdl/icache.vhdl (and libre-soc's dcache.py/icache.py) as well as the soc.vhdl 64-to-32 adapter, are perfectly fine | 11:21 |
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| openpowerbot | [mattermost] <lkcl> WB4-pipeline-mode looks like it is just something that the FOSS HDL community has not really used. litex avoids the problem with the trick "stall = cyc & ~ack" but for some reason this is insufficient for nmigen-soc and lambdasoc | 11:23 |
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