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| openpowerbot_ | [slack] <Paul Mackerras> lkcl, yes the icache tlb is async at present | 07:07 |
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| openpowerbot_ | [slack] <Paul Mackerras> ideally one itlb lookup should be good for several fetches - if we store the most recent itlb entry used, we should be able to reduce the itlb access rate and thus make the itlb a synchronous RAM | 07:09 |
| openpowerbot_ | [slack] <Paul Mackerras> I'd really like to be able to put the itlb in block RAM... | 07:10 |
| openpowerbot_ | [mattermost] <lkcl> it's done (i believe) in dcache? | 13:57 |
| openpowerbot_ | [mattermost] <lkcl> https://github.com/antonblanchard/microwatt/blob/master/dcache.vhdl#L617 | 15:50 |
| openpowerbot_ | [mattermost] <lkcl> dtlb_reads: if rising_edge(clk) then | 15:50 |
| openpowerbot_ | [mattermost] <lkcl> https://github.com/antonblanchard/microwatt/blob/master/dcache.vhdl#L711 | 15:51 |
| openpowerbot_ | [mattermost] <lkcl> tlb_update: if rising_edge(clk) then | 15:51 |
| openpowerbot_ | [mattermost] <lkcl> and in dcache.py i did put that into its own separate module, which then i was able to use a nmigen Memory(), which has standard 1-clock synchronous read/write access (because dtlb_reads and dtlb_update both have those rising_edge()), and blah blah) | 15:52 |
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