| openpowerbot | [slack] <Anton Blanchard> I've worked with tgingold to fix some ghdl Verilog synthesis issues. Mainline ghdl now synthesizes working Verilog for microwatt using `ghdl --synth --out=verilog` avoiding the requirement for yosys and the ghdl plugin. We'll still use yosys for FPGA builds, but for the ASIC flow or verilator and icarus verilog simulation, the ghdl output works. | 06:55 |
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| openpowerbot | [slack] <joel> > We'll still use yosys for FPGA builds | 07:03 |
| openpowerbot | [slack] <joel> @Anton Blanchard Is this because it's used in the FPGA flow regardless? | 07:03 |
| openpowerbot | [slack] <Anton Blanchard> Yeah. One day the ASIC flow might integrate VHDL directly (via the GHDL plugin), but for now we have to do some modification of the Verilog for plumbing power in. | 07:08 |
| openpowerbot | [slack] <joel> I see, so it's more about wanting to do some changes to the verilog than eliminating yosys from the flow | 07:11 |
| openpowerbot | [slack] <Anton Blanchard> Yep. Avoiding Yosys for Verilator and Icarus Verilog simulation simplifies things a bit. It also simulates faster, possibly because the Verilog output from ghdl is higher level. | 07:19 |
| lkcl | Anton: is it also more "meaningful"? the yosys-ghdl-plugin is... well... pretty awful: it trashes VHDL records, converts everything to anonymous bits with virtually no recogniseable names from the original VHDL | 20:50 |
| lkcl | also, you may be interested to know that coriolis2 automatically adds VSS/VDD to all Cells, automatically | 20:51 |
| lkcl | although it converts VHDL-yosys-BLIF-{VHDL-subset} the process is fully automated | 20:51 |
| lkcl | the VHDL-subset is at the "Cell-only" bit-level | 20:52 |
| lkcl | but at the same time the conversion to VHDL-subset takes the opportunity to add all and any missing VSS/VDD | 20:52 |
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