| openpowerbot | [mattermost] <lkcl> Todd, Anton, Manikandan: the IO pads are entirely controlled by the "management" processor, which performs GPIO "muxing". by holding RESET, those muxes will be set to their default and held there. if you are *very lucky* those defaults will be to route the IO pads *away* from the "management" processor, towards the "user" GDS-II area. | 13:42 |
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| openpowerbot | [mattermost] <lkcl> the other thing you may have to watch out for: it's highly possible that the PLL will also be held in the same reset. | 13:42 |
| openpowerbot | [mattermost] <lkcl> "The MPW1 shuttle is terminally broken due to an issue in the Caravel chip. " - this can be "fixed" by changing the supply voltage (over-volting i believe). someone did actually do it | 13:43 |
| openpowerbot | [mattermost] <lkcl> "What is the frequency of operation, maximum frequency of microwatt ASIC?" - there is a limit of 60 mhz on the IO pads caused by routing of GPIO through the "management" core | 13:44 |
| openpowerbot | [mattermost] <lkcl> "We havent simulated Linux on the ASIC directly (too slow)," - i have a microwatt_verilator branch which takes appx 4-6 hours to get to the same boot prompt that joel shenki got to | 13:45 |
| openpowerbot | [mattermost] <lkcl> https://git.libre-soc.org/?p=microwatt.git;a=shortlog;h=refs/heads/verilator_trace | 13:46 |
| openpowerbot | [mattermost] <lkcl> works great, but uses an older version because the older version of microwatt is much simpler and i'm still extracting information from it | 13:46 |
| openpowerbot | [mattermost] <lkcl> as i mentioned 18+ months ago, many of the optimisations added to microwatt unfortunately actively interfere with its readability and understandability as a Reference Design for Power ISA. | 13:47 |
| openpowerbot | [mattermost] <lkcl> rather unfortunate because obviously there's a compelling need to improve both performance and reduce resource usage (in both FPGA and ASIC) | 13:48 |
| openpowerbot | [mattermost] <lkcl> also, Anton: you may be interested to know that Professor Galayko will be working on porting the Libre-SOC / NLnet sponsored PLL (developed in TSMC 180nm) to sky130 | 13:49 |
| openpowerbot | [mattermost] <lkcl> the lack of a PLL (and IO pad cells) is the primary reason why the "management" core is "attractive" | 13:50 |
| openpowerbot | [mattermost] <lkcl> i and others have mentioned repeatedly (and it's been ignored) that there does exist a real need for full access to the entire 15 mm^2 area | 13:51 |
| openpowerbot | [mattermost] <lkcl> the answer given has always been "it's too much work" | 13:52 |
| openpowerbot | [mattermost] <lkcl> ChipIgnite exists and is USD 9,500 and has full access to the entire 15 mm^2 | 13:53 |
| openpowerbot | [mattermost] <lkcl> therefore *in theory* it would be possible to utilise Professor Galayko's PLL, with a microwatt core, but you'd need to define your own GPIO. all of which would be much easier with coriolis2 because it's set up to auto-generate the IO Ring, deals with VSS/VDD separately from IOVSS/IOVDD, deals with Clock H-Trees, deals with high-density routing, correctly allocates buffers and antenna, etc. etc. etc. etc. | 14:05 |
| openpowerbot | [mattermost] <lkcl> the only caveat being that Jean-Paul Chaput hasn't yet added the impedance analysis needed for 130nm yet (which isn't necessary for the more-than-bullet-proof 180nm), that's on the TODO list | 14:06 |
| openpowerbot | [mattermost] <lkcl> but | 14:06 |
| openpowerbot | [mattermost] <lkcl> LIP6 has an Academic License for Cadence DRC so in theeeorrryy could run a design through that, just to make sure | 14:06 |
| * openpowerbot [mattermost] <lkcl> waves to rosedahl | 19:51 | |
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