Monday, 2020-09-28

mePy2[m]What are these?00:17
lkclskywater 130nm PDK cells11:36
lkcland the layout for the 180nm ASIC including the first preliminary ioring11:36
dcz_are different layers represented by different colors?13:33
lkcldcz_, : yes.  4 metal tracks, 2 horizontal 2 vertical plus VCC and VSS (power ground)14:49
dcz_I'm just surprised to see a lot of uniform black/beige areas on this:
lkcl1st iteration14:55
lkcldcz_: 2nd iteration
dcz_now this looks like some transistors!15:04
lkclthe io ring pads are enormous transistors15:05
lkcleach blue bit is what the gold bond wire is smashed onto, hard enough to melt the gold and fuse it with the pad15:06
lkcltoday however, the main difference is: i worked out how to tell coriolis2 to connect up from the IO pads to the actual core.15:09
mePy2[m]lkcl: I would have liked to make a working, nice looking circuit. one for each image.19:34
mePy2[m]But I am been having a hard time doing it.19:35
mePy2[m] * But I have been having a hard time doing it.19:35
mePy2[m]I tried using CircuitVerse and SimcirJS. They both need some code modification in my opinion, in order to make them work as I want it to do.19:37
mePy2[m]Also to make the circuit works, I should need to build the latches, Computation unit, the little cylinder at the bottom.19:39
mePy2[m]Which I do not really know how they are made inside...19:40
mePy2[m]What do you suggest me to do?19:40
mePy2[m]I would like to make this work.19:40
mePy2[m]But at the same time, I would spend this time by making the “simple” SVG images instead.19:41
lkcltiny circle means "invert"21:41
lkclflat edged thing is an AND gate21:41
lkclconcave edged thing is an OR gate21:42
lkcltherefore concave-with-a-tiny circle is a NOR gate21:42
lkcllook them up on that wikipedia "logic gate" page21:42
lkclthe cylinder thing can be effectively ignored21:43
mePy2[m]I know the basic things. But starting from them, I would like to actually make and test/play with the circuit :D21:43
lkclbasically it's a way to make sure that the "request release" signal goes valid at exactly the same time as the result from the "Computation" block21:44
lkclwell, if you make the computation block say... a XOR gate (a single XOR)21:44
lkclmake op1 and op2 only 1 bit wide21:45
lkcland use a DFF as a substitute for the latches21:45
lkclthat should do the trick, i think21:45
lkclgimme a sec to look it up21:46
lkclnope not a DFF21:46
lkcl1 sec21:46
lkclmight be a D-Latch21:49
lkclit's Draw Menu | Digital Chips | Add Latch21:57
lkcland i can see "Add Full Adder" as well so you could construct a 4-bit adder21:58
mePy2[m]But that would not be the one used by the project21:59
mePy2[m]I would like to make something useful too. In this case the circuits21:59
mePy2[m]The ones from the images21:59
mePy2[m]But thank you. For sure in this way I will understand the basics22:00
lkclyes, the long rectangle with the triangle is, in falstad circuitjs, "Latch".22:00
lkclunder Digital Chips menu22:00
mePy2[m]Nice nice22:00
mePy2[m]Mhm we could make the images from fastlab22:00
lkcland the "Computation" block can be "anything you want"22:01
mePy2[m]Maybe there is a way to get the SVG22:01
mePy2[m]I shall try22:01
lkclGWT can actually "construct" SVG images22:08
lkclcircuitjs is written with GWT (google web toolkit)22:08
lkclin theeoorryyy it would be possible to actually get circuitjs to actually create the SVG image22:08
lkclwhich would be awesomely cool22:08
mePy2[m]I mean, I could draw the images there22:11
mePy2[m]But still I would prefer to first choose the “final” solution22:12
mePy2[m]If we want only images, it is fine.22:12
mePy2[m]But I would like a real time simulator too :’(22:12
mePy2[m]An interactive webpage22:13
mePy2[m]Who knows... does it make sense at all? Mhm22:13
lkclyehyeh, i'd really like to see that page have embedded versions of the actual circuits22:15
mePy2[m]Me too!22:21

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