| mePy2[m] | What are these? | 00:17 |
|---|---|---|
| lkcl | skywater 130nm PDK cells | 11:36 |
| lkcl | and the layout for the 180nm ASIC including the first preliminary ioring | 11:36 |
| dcz_ | are different layers represented by different colors? | 13:33 |
| lkcl | dcz_, : yes. 4 metal tracks, 2 horizontal 2 vertical plus VCC and VSS (power ground) | 14:49 |
| dcz_ | I'm just surprised to see a lot of uniform black/beige areas on this: https://libre-soc.org/180nm_Oct2020/2020-09-27_23-12.png | 14:50 |
| lkcl | 1st iteration | 14:55 |
| lkcl | dcz_: 2nd iteration https://libre-soc.org/180nm_Oct2020/2020-09-28_15-02.png | 15:03 |
| dcz_ | now this looks like some transistors! | 15:04 |
| lkcl | the io ring pads are enormous transistors | 15:05 |
| lkcl | each blue bit is what the gold bond wire is smashed onto, hard enough to melt the gold and fuse it with the pad | 15:06 |
| lkcl | today however, the main difference is: i worked out how to tell coriolis2 to connect up from the IO pads to the actual core. | 15:09 |
| mePy2[m] | lkcl: I would have liked to make a working, nice looking circuit. one for each image. | 19:34 |
| mePy2[m] | But I am been having a hard time doing it. | 19:35 |
| mePy2[m] | * But I have been having a hard time doing it. | 19:35 |
| mePy2[m] | I tried using CircuitVerse and SimcirJS. They both need some code modification in my opinion, in order to make them work as I want it to do. | 19:37 |
| mePy2[m] | Also to make the circuit works, I should need to build the latches, Computation unit, the little cylinder at the bottom. | 19:39 |
| mePy2[m] | Which I do not really know how they are made inside... | 19:40 |
| mePy2[m] | What do you suggest me to do? | 19:40 |
| mePy2[m] | I would like to make this work. | 19:40 |
| mePy2[m] | But at the same time, I would spend this time by making the “simple” SVG images instead. | 19:41 |
| lkcl | tiny circle means "invert" | 21:41 |
| lkcl | flat edged thing is an AND gate | 21:41 |
| lkcl | concave edged thing is an OR gate | 21:42 |
| lkcl | therefore concave-with-a-tiny circle is a NOR gate | 21:42 |
| lkcl | look them up on that wikipedia "logic gate" page | 21:42 |
| lkcl | the cylinder thing can be effectively ignored | 21:43 |
| mePy2[m] | Yeah | 21:43 |
| mePy2[m] | I know the basic things. But starting from them, I would like to actually make and test/play with the circuit :D | 21:43 |
| lkcl | basically it's a way to make sure that the "request release" signal goes valid at exactly the same time as the result from the "Computation" block | 21:44 |
| lkcl | :) | 21:44 |
| lkcl | well, if you make the computation block say... a XOR gate (a single XOR) | 21:44 |
| lkcl | make op1 and op2 only 1 bit wide | 21:45 |
| lkcl | and use a DFF as a substitute for the latches | 21:45 |
| lkcl | that should do the trick, i think | 21:45 |
| lkcl | gimme a sec to look it up | 21:46 |
| lkcl | https://www.electronics-tutorials.ws/sequential/seq_4.html | 21:46 |
| lkcl | nope not a DFF | 21:46 |
| lkcl | 1 sec | 21:46 |
| lkcl | might be a D-Latch | 21:49 |
| lkcl | in https://www.falstad.com/circuit/ | 21:56 |
| lkcl | it's Draw Menu | Digital Chips | Add Latch | 21:57 |
| lkcl | and i can see "Add Full Adder" as well so you could construct a 4-bit adder | 21:58 |
| mePy2[m] | Mhm | 21:59 |
| mePy2[m] | But that would not be the one used by the project | 21:59 |
| mePy2[m] | I would like to make something useful too. In this case the circuits | 21:59 |
| mePy2[m] | The ones from the images | 21:59 |
| mePy2[m] | But thank you. For sure in this way I will understand the basics | 22:00 |
| lkcl | yes, the long rectangle with the triangle is, in falstad circuitjs, "Latch". | 22:00 |
| lkcl | under Digital Chips menu | 22:00 |
| mePy2[m] | Nice nice | 22:00 |
| mePy2[m] | Mhm we could make the images from fastlab | 22:00 |
| lkcl | and the "Computation" block can be "anything you want" | 22:01 |
| mePy2[m] | Maybe there is a way to get the SVG | 22:01 |
| mePy2[m] | I shall try | 22:01 |
| lkcl | GWT can actually "construct" SVG images | 22:08 |
| lkcl | circuitjs is written with GWT (google web toolkit) | 22:08 |
| lkcl | in theeoorryyy it would be possible to actually get circuitjs to actually create the SVG image | 22:08 |
| lkcl | which would be awesomely cool | 22:08 |
| mePy2[m] | Yeah | 22:11 |
| mePy2[m] | I mean, I could draw the images there | 22:11 |
| mePy2[m] | But still I would prefer to first choose the “final” solution | 22:12 |
| mePy2[m] | If we want only images, it is fine. | 22:12 |
| mePy2[m] | But I would like a real time simulator too :’( | 22:12 |
| mePy2[m] | An interactive webpage | 22:13 |
| mePy2[m] | Who knows... does it make sense at all? Mhm | 22:13 |
| lkcl | yehyeh, i'd really like to see that page https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ have embedded versions of the actual circuits | 22:15 |
| mePy2[m] | Me too! | 22:21 |
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