| lkcl | good | 12:13 |
|---|---|---|
| lkcl | you make something up. | 12:13 |
| lkcl | make it... an XOR gate. | 12:13 |
| lkcl | anything. | 12:13 |
| lkcl | make op1 1 bit only, make op2 1 bit only, and make "computation block" equal to "one single XOR gate". | 12:14 |
| lkcl | however | 12:14 |
| lkcl | this makes the design "not really look like the diagram", doesn't it? | 12:14 |
| lkcl | which make simcirjs not exactly the best "final" choice but still a good start for experimenting | 12:15 |
| lkcl | really (like in that 16-bit CPU) "computation block" qualifies as a "sub-circuit with its own black-box-style inputs and outputs" doesn't it? | 12:21 |
| lkcl | and i don't believe simcirjs can do "sub-circuits", or can it? | 12:22 |
| mePy2[m] | Yeah | 14:00 |
| mePy2[m] | Nice anyway! Can’t wait to have some time to make it :D | 14:00 |
| lkcl | :) | 14:12 |
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