| AndrewR | Hello everyone. I have recently stumbled upon the libre-soc project, and would really like to contribute, although it probably won't happen any time soon. | 09:50 |
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| AndrewR | Unfortunately, I don't have neither HDL design experience nor Python knowledge. I'm more from the software background, but I'm looking forward to learn the hardware stuff. | 09:52 |
| AndrewR | I've been looking through the wiki and I don't quite understand what kind of ISA will be used in the end, since some pages mention RISC-V, and others talk about the POWER ISA. | 09:55 |
| AndrewR | This page https://libre-soc.org/openpower/ even mentions about dual ISA. Can someone point me to the right page on the wiki? | 09:56 |
| AndrewR | Also, this page https://libre-soc.org/discussion/ mentions RISC-V as "Fake Open Source". What does it mean? | 09:58 |
| lkcl | AndrewR: welcome | 18:19 |
| lkcl | yeah you'll be fascinated to know that IBM requires c++ experience for working on its HDL | 18:19 |
| lkcl | and that's because they develop their own synthesis and simulation tools | 18:20 |
| lkcl | which are far in advance of anything commercially available (Mentor, Synopsis) | 18:21 |
| lkcl | given that those are $100 million licensing costs that's saying something | 18:21 |
| lkcl | the project started out mid-2018 after RISC-V began to take off | 18:21 |
| lkcl | 18 months development and design effort began, to prepare the ISA enhancements needed for making RISC-V hybrid CPU-GPU | 18:22 |
| lkcl | at the same time, due to NLnet funding transparency requirements, i approached the RISC-V Foundation and requested to join the Foundation without completely compromising the business objectives (full transparency for security and audit reasons) and without the conflict of interest with our funding body. | 18:23 |
| lkcl | i received not one single response, in 18 months. | 18:24 |
| lkcl | we conclude, therefore, that RISC-V is not open, at all. it's "open as long as you are a billion-dollar company such as google, qualcomm or nvidia" | 18:25 |
| lkcl | it's also "open as long as you do not wish to innovate" | 18:26 |
| lkcl | the EU Commission has been notified, because it's not just a violation of Trademark Law, they're acting anti-competitively and also have wasted EU funding because we have had to abandon huge amounts of work | 18:27 |
| lkcl | since the decision to go with OpenPOWER, a huge s***-storm went down and they opened up some of the mailing lists that were formerly completely closed and only accessible once you'd compromised and signed the Membership Agreement. | 18:28 |
| lkcl | so, as a small team that's on a tight deadline, we haven't had time to go through every single page on the wiki and modify it. | 18:30 |
| AndrewR | wow, thanks for this clarification. I also would like to clarify about "180nm Oct2020" and "45nm Fall2022" tapeouts. Are these different projects, or the latter one is a continuation of the former? | 18:55 |
| AndrewR | If they are different projects, how do they relate to each other? | 18:56 |
| lkcl | we have "learn to walk before run". | 20:39 |
| lkcl | plus, think about it: would you bet on a team that had never done an ASIC design before? let alone using a completely untested python-based HDL! | 20:40 |
| lkcl | so we do 180nm first, iterate on that - @ only EUR 600 per sq.mm | 20:40 |
| lkcl | *then* when we have working designs crank it up. | 20:41 |
| lkcl | it'll be the same ISA, the same basic design, just with the python-based parameters "dialled up" | 20:42 |
| lkcl | for example there's a python dictionary that specifies the number of each type of Function Unit | 20:42 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits/compunits.py;h=096cda34f4a5974ecdd9cc93c454e595765a3192;hb=c47427ce770a8b59c3e47a7e37fdbc30c959ab53#l246 | 20:43 |
| lkcl | in the 180nm test chip, surpriiiise! those will all be 1 | 20:43 |
| lkcl | and in a quad-core SMP version, surpriiiise! they'll all be dialed up. | 20:44 |
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