Sunday, 2020-10-11

AndrewRHello everyone. I have recently stumbled upon the libre-soc project, and would really like to contribute, although it probably won't happen any time soon.09:50
AndrewRUnfortunately, I don't have neither HDL design experience nor Python knowledge. I'm more from the software background, but I'm looking forward to learn the hardware stuff.09:52
AndrewRI've been looking through the wiki and I don't quite understand what kind of ISA will be used in the end, since some pages mention RISC-V, and others talk about the POWER ISA.09:55
AndrewRThis page even mentions about dual ISA. Can someone point me to the right page on the wiki?09:56
AndrewRAlso, this page mentions RISC-V as "Fake Open Source". What does it mean?09:58
lkclAndrewR: welcome18:19
lkclyeah you'll be fascinated to know that IBM requires c++ experience for working on its HDL18:19
lkcland that's because they develop their own synthesis and simulation tools18:20
lkclwhich are far in advance of anything commercially available (Mentor, Synopsis)18:21
lkclgiven that those are $100 million licensing costs that's saying something18:21
lkclthe project started out mid-2018 after RISC-V began to take off18:21
lkcl18 months development and design effort began, to prepare the ISA enhancements needed for making RISC-V hybrid CPU-GPU18:22
lkclat the same time, due to NLnet funding transparency requirements, i approached the RISC-V Foundation and requested to join the Foundation without completely compromising the business objectives (full transparency for security and audit reasons) and without the conflict of interest with our funding body.18:23
lkcli received not one single response, in 18 months.18:24
lkclwe conclude, therefore, that RISC-V is not open, at all.  it's "open as long as you are a billion-dollar company such as google, qualcomm or nvidia"18:25
lkclit's also "open as long as you do not wish to innovate"18:26
lkclthe EU Commission has been notified, because it's not just a violation of Trademark Law, they're acting anti-competitively and also have wasted EU funding because we have had to abandon huge amounts of work18:27
lkclsince the decision to go with OpenPOWER, a huge s***-storm went down and they opened up some of the mailing lists that were formerly completely closed and only accessible once you'd compromised and signed the Membership Agreement.18:28
lkclso, as a small team that's on a tight deadline, we haven't had time to go through every single page on the wiki and modify it.18:30
AndrewRwow, thanks for this clarification. I also would like to clarify about "180nm Oct2020" and "45nm Fall2022" tapeouts. Are these different projects, or the latter one is a continuation of the former?18:55
AndrewRIf they are different projects, how do they relate to each other?18:56
lkclwe have "learn to walk before run".20:39
lkclplus, think about it: would you bet on a team that had never done an ASIC design before? let alone using a completely untested python-based HDL!20:40
lkclso we do 180nm first, iterate on that - @ only EUR 600 per sq.mm20:40
lkcl*then* when we have working designs crank it up.20:41
lkclit'll be the same ISA, the same basic design, just with the python-based parameters "dialled up"20:42
lkclfor example there's a python dictionary that specifies the number of each type of Function Unit20:42
lkclin the 180nm test chip, surpriiiise! those will all be 120:43
lkcland in a quad-core SMP version, surpriiiise! they'll all be dialed up.20:44

Generated by 2.17.1 by Marius Gedminas - find it at!