| colepoirier_ | lkcl: sure, is this indicated by "Memtest OK" ? | 00:16 |
|---|---|---|
| colepoirier_ | interestingly for 12.5MHz it prints 'initializing memory' | 00:29 |
| colepoirier_ | but for 25MHz it just jumps right into memtest and then memspeed | 00:30 |
| colepoirier_ | both are uploaded to ftp server | 00:34 |
| lkcl | colepoirier_: yes, we want "Memtest ok" after the scrolling-thing | 00:42 |
| lkcl | ah excellent so 25mhz is working, but 12.5mhz is not | 00:43 |
| lkcl | that's really good, it means that if we absolutely have to we stand a chance of running the ASIC as low as 25mhz and still being able to connect to SDRAM at that speed | 00:44 |
| colepoirier_ | to clarify, 12.5MHz is 'Memtest OK' as well | 03:49 |
| colepoirier_ | Just it prints out 'initializing memory' whereas 25MHz skips it | 03:50 |
| lkcl | errr that's weird, it shouldn't | 10:32 |
| lkcl | but hey | 10:34 |
| *** colepoirier_ is now known as colepoirier | 16:45 | |
| colepoirier | Yeah I'm not sure why it does that but both pass memtest and memspeed | 16:51 |
| lkcl | awesome. now of course i'm wondering if the dram clock actually comes _from_ the main clock | 17:03 |
| lkcl | looking at the PLL code in ulx3s.py target | 17:08 |
| lkcl | https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/ulx3s.py#L60 | 17:08 |
| lkcl | i think it does | 17:08 |
| colepoirier | Cool! | 17:19 |
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