Friday, 2020-10-30

colepoirier_lkcl: sure, is this indicated by "Memtest OK" ?00:16
colepoirier_interestingly for 12.5MHz it prints 'initializing memory'00:29
colepoirier_but for 25MHz it just jumps right into memtest and then memspeed00:30
colepoirier_both are uploaded to ftp server00:34
lkclcolepoirier_: yes, we want "Memtest ok" after the scrolling-thing00:42
lkclah excellent so 25mhz is working, but 12.5mhz is not00:43
lkclthat's really good, it means that if we absolutely have to we stand a chance of running the ASIC as low as 25mhz and still being able to connect to SDRAM at that speed00:44
colepoirier_to clarify, 12.5MHz is 'Memtest OK' as well03:49
colepoirier_Just it prints out 'initializing memory' whereas 25MHz skips it03:50
lkclerrr that's weird, it shouldn't10:32
lkclbut hey10:34
*** colepoirier_ is now known as colepoirier16:45
colepoirierYeah I'm not sure why it does that but both pass memtest and memspeed16:51
lkclawesome.  now of course i'm wondering if the dram clock actually comes _from_ the main clock17:03
lkcllooking at the PLL code in target17:08
lkcli think it does17:08

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