| programmerjake[m | happy new years/new years eve! | 03:20 |
|---|---|---|
| mePy2[m] | Happy new year! | 10:58 |
| lkcl | happy new year :) | 17:57 |
| programmerjake[m | a new year, new patents expire, x86_64+OpenPower CPU? :P | 18:25 |
| programmerjake[m | maybe later... | 18:25 |
| lkcl | mmm... x86 variable-length byte-level decoding, mmmm fuuun :) | 18:27 |
| lkcl | mind you if we did what China ICT did with the Loongson G architecture (just implement the top 200 instructions) | 18:28 |
| lkcl | we'd end up, like them, with 70% performance under qemu JIT :) | 18:29 |
| programmerjake[m | i was thinking just x86 32-bit user mode (with just enough support for segment registers to support wine & linux) and 64-bit user mode with openpower kernel mode and boots in openpower mode | 18:31 |
| programmerjake[m | if we're depending on qemu, total-store-order memory ordering is probably sufficient -- what the apple m1 does iirc | 18:32 |
| programmerjake[m | no need to implement an x86 decoder if we're using qemu jit | 18:33 |
| programmerjake[m | no 16-bit, no v86 mode, no priveleged-only regs | 18:35 |
| lkcl | mitch alsup showed me how to do TSO | 22:13 |
| lkcl | is there a list somewhere of the opcodes you're thinking of? | 22:13 |
| sorear | loongson does not implement "opcodes", but you know that | 22:14 |
| lkcl | sorear: i didn't - i'd heard the story of what ICT did, but don't know the full details | 22:15 |
| lkcl | i have a vague recollection of someone telling me that they focussed on FP x86 | 22:16 |
| lkcl | http://cs.brown.edu/courses/cs033/docs/guides/x64_cheatsheet.pdf | 22:16 |
| sorear | it has a bunch of custom instructions in the MIPS encoding to make qemu faster | 22:17 |
| lkcl | ooer i am getting flashbacks to when i worked for CEDAR Audio. had to do 80386 assembly-level programming :) | 22:17 |
| lkcl | sorear: ahh thank you. | 22:17 |
| lkcl | so that's how they did it. interesting | 22:18 |
| sorear | most importantly variants of arithmetic instructions that calculate x86 flags (including PF and AF) and a software-exposed CAM for mapping x86 program counters to translated program counters | 22:18 |
| sorear | very curious how rosetta2 handles pf/af | 22:18 |
| lkcl | uh-oh https://wiki.osdev.org/X86-64_Instruction_Encoding | 22:22 |
| lkcl | optional and mandatory prefixes of between 1-4 bytes? | 22:22 |
| * lkcl cackles manically | 22:22 | |
| sorear | https://www.researchgate.net/profile/Guo-Jie_Li/publication/338169924_Godson-3/links/5e046efa4585159aa49ab28d/Godson-3.pdf | 22:24 |
| lkcl | sorear: thx | 22:25 |
| lkcl | yowser. "software simulation of the 6-bit EFlags with MIPS instructions requires *tens* of MIPS instructions" | 22:27 |
| lkcl | dang | 22:27 |
| programmerjake[m | if we wanted to have fast qemu x86 on openpower, we'd also want to support the f128 extension, since it has instructions for fast emulation of f80 | 23:04 |
| programmerjake[m | in particular: f80 alu ops can be emulated by doing a f128 op in round-to-odd mode, then a round to f80 instruction in the desired rounding mode | 23:06 |
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