Sunday, 2021-04-25

*** cesar[m]11 is now known as cesar[m]100:57
cesar[m]1lkcl: OK, I think I'm done with the SVP64 CR predication. I'm ready to work on dcache. What do you need?21:56
*** gatecat <gatecat!sid281702@gateway/web/> has left #libre-soc21:57
lkclcesar[m]1, fantastic.  i've a case committed (very recently)22:00
lkclthe wb_in.stall, if set, results in requests that come one cycle too late22:01
lkclcomment out line 164822:02
lkcland you will see that dcache rams wr_data and wr_addr are one cycle out of sync22:03
cesar[m]1Sure, I'll take a look.22:06
cesar[m]1By the way, I'm having a new error on this test:22:08
cesar[m]1python ~/src/openpower-isa/src/openpower/decoder/isa/ DecoderTestCase.test_cmpeqb22:08
cesar[m]1File "/home/cstrauss/src/openpower-isa/src/openpower/decoder/isa/", line 99, in op_cmpeqb22:09
cesar[m]1src1 = GPR[RA]22:09
cesar[m]1NameError: name 'RA' is not defined22:09
lkclcesar[m]1: remove the entirety of the pseudo-code from pywriter22:10
lkcluse the new openpower-isa repo22:10
lkcland re-run "make pywriter", there22:11
lkcllet me run that here and see if it happens22:11
lkclthat's running now22:12
lkclcesar[m]1: no, doesn't happen here.  does give a silly error22:14
lkcl  File "openpower/decoder/isa/", line 320, in test_mtcrf22:14
lkcl    self.assertEqual(, SelectableInt(expected << ((7-i)*4), 32))22:14
lkclwhich i kinda expected22:14
cesar[m]1I fixed this earlier today, please do a git pull.22:17
cesar[m]1... on the openpower-isa repo.22:18
lkclah, star22:19
lkclbrilliant, you got up-to-date on the new openpower-isa repo, yay22:20
lkclok, so, dcache.22:20
lkclthe test, what it does is: it a load at address 6*822:21
lkcl(line 1798, 1806)22:21
lkclthat is actually where the problem occurs, straight away.22:21
lkclactually i will commit a comment-out of the dcache_store 1 sec22:22
lkclwhat dcache does is, when it sees a load request, it actually fires off *eight* 64-bit requests22:23
lkclto fill the entire cache line22:23
lkcleach of those 8 loads, the result is written into the sram.22:25
lkclin this case, it is replace_way=0b10 (2nd sram - there are 4).  you can see do_wr1 is set to 122:26
lkclyou can also see, wr_data is *one cycle early* from the wr_data22:26
lkclat line 112922:28
lkclline 1330, r1.store_row.eq(req_row) - req_row is delayed by 1 clock cycle22:36
lkclcesar[m]1, i think i have it.  it is to do with r1.real_adr at line 142423:00
lkcloh btw, there is a major bug in microwatt, long-standing23:17
lkclcesar[m]1: all wishbone addresses are 64-bit *include the three LSBs* which should never be done23:18
lkclthe "sel" lines are supposed to be used to specify the bytes, effectively encoding the three LSBs of the address in unary23:18
lkclbut, in microwatt, what they have done is mistakenly put the 3 LSBs onto the address bus23:19
lkclbut this is *consistent* across *all* code23:19
lkcltherefore, it "works".23:19
lkclin litex, those 3 LSBs are set to zeros, externally.23:19
lkclthe WB spec says, if you have a 64-bit data bus, and 32-bit addresses, you should only put (32-(64//8)) bits onto the WB bus.23:20
lkclmicrowatt puts 32.23:20
cesar[m]1Interesting. Are those 3 LSB bits decoded at all on the slave, or simply ignored / not connected?23:22
lkclinside microwatt?23:22
lkclthey should never have been there in the first place23:22
lkcli am *hoping* they are not used accidentally as "state" information23:23
lkclROW_LINE_BITS is set to 3 (which is the 3 LSBs)23:24
lkclactually... 1 sec23:25
lkclneed to create something called ROW_SIZE_BITS23:25
programmerjake> the WB spec says, if you have a 64-bit data bus, and 32-bit addresses, you should only put (32-(64//8)) bits onto the WB bus.23:27
programmerjakeisn't that actually (32-log2(64/8)) bits?23:27
lkclprogrammerjake, yes, thank you, good catch23:27
lkclok, late here. been at this a while. night all23:51

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