| Chips4Makers[m] | lkcl, choozy : Current plan is to get 160 chips made for the 180nm tape-out. There is no difference in yield between MPW and full mask set production; I only expect a few of them failing. | 12:52 |
|---|---|---|
| lkcl | Chips4Makers[m], great! | 14:13 |
| lkcl | Chips4Makers[m]: according to kbeckmann on #nmigen, caravel (not carav*an*, carav*el*) gives direct access to the IO pads | 14:46 |
| lkcl | i'm trying to ascertain more details to see if it's suitable | 14:55 |
| lkcl | Chips4Makers[m]: Phillip Guthrie points out in #skywater-pdk that as long as the GDS-II files meet the exact placement positions of the Google MPW2 shuttle runs, we should be able to use FlexLib IOPads. | 16:00 |
| lkcl | which is cool! | 16:00 |
| lkcl | i'm testing the concept "can we get free 130nm tape-outs yet still use FlexLib and coriolis2" | 16:06 |
| jn__ | pushing the envelope of free hardware design! :) | 16:07 |
| lkcl | cesar[m]1: wha-hey! i have a misaligned exception 0x600 raised in ISACaller | 16:15 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=08a4ab72c2f7af84acea715b06285b0496c4a416 | 16:15 |
| Chips4Makers[m] | @lkcl: I also did not commit to reach the deadline for this submission no.2 for both IO and SRAM design. | 17:06 |
| lkcl | Chips4Makers[m]: understood. ah yes, sorry. nuts. i forgot to consult you about that | 17:34 |
| lkcl | keenly aware we haven't had the crypto-router NLnet grant approved / announced yet | 17:36 |
| lkcl | so just to be clear, this is all provisional | 17:36 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!