Monday, 2021-05-10

Chips4Makers[m]lkcl, choozy : Current plan is to get 160 chips made for the 180nm tape-out. There is no difference in yield between MPW and full mask set production; I only expect a few of them failing.12:52
lkclChips4Makers[m], great!14:13
lkclChips4Makers[m]: according to kbeckmann on #nmigen, caravel (not carav*an*, carav*el*) gives direct access to the IO pads14:46
lkcli'm trying to ascertain more details to see if it's suitable14:55
lkclChips4Makers[m]: Phillip Guthrie points out in #skywater-pdk that as long as the GDS-II files meet the exact placement positions of the Google MPW2 shuttle runs, we should be able to use FlexLib IOPads.16:00
lkclwhich is cool!16:00
lkcli'm testing the concept "can we get free 130nm tape-outs yet still use FlexLib and coriolis2"16:06
jn__pushing the envelope of free hardware design! :)16:07
lkclcesar[m]1: wha-hey! i have a misaligned exception 0x600 raised in ISACaller16:15
Chips4Makers[m]@lkcl: I also did not commit to reach the deadline for this submission no.2 for both IO and SRAM design.17:06
lkclChips4Makers[m]: understood.  ah yes, sorry.  nuts.  i forgot to consult you about that17:34
lkclkeenly aware we haven't had the crypto-router NLnet grant approved / announced yet17:36
lkclso just to be clear, this is all provisional17:36

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