Friday, 2021-07-02

lkcli got a demo running of how to remap the triple loop of matrix multiply into 3 linear array "generators"
lkclthe idea is to drop that onto the "normally linear Vector operations"00:05
lkcland if done on top of FMAC it does an arbitrary-sized Matrix Multiply *in-place*, up to a total of 64 FMACs00:06
lkclthe generators however i am really struggling to get the ordering right00:07
lkcli mean, they're right _now_ because i went through dozens of permutations of arguments until the right sequence(s) were printed00:07
lkcla review would be helpful00:08
*** Shell <Shell!~shell@user/shell> has left #libre-soc08:18
sasi8985Hi all, I am trying to build Libresoc on ubuntu;i tried on mintos 20.x it worked but for ubuntu i am getting this error10:43
sasi8985Traceback (most recent call last):10:43
sasi8985  File "src/soc/simple/", line 117, in <module>10:43
sasi8985    vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")10:43
sasi8985  File "/tmp/soc/nmigen/nmigen/back/", line 61, in convert10:43
sasi8985    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)10:43
sasi8985  File "/tmp/soc/nmigen/nmigen/back/", line 47, in _convert_rtlil_text10:43
sasi8985    return["-q", "-"], "\n".join(script),10:43
sasi8985  File "/tmp/soc/nmigen/nmigen/_toolchain/", line 145, in run10:43
sasi8985    return cls._process_result(popen.returncode, stdout, stderr, ignore_warnings, src_loc_at)10:43
sasi8985  File "/tmp/soc/nmigen/nmigen/_toolchain/", line 108, in _process_result10:43
sasi8985    raise YosysError(stderr.strip())10:43
sasi8985nmigen._toolchain.yosys.YosysError: thread '<unnamed>' panicked at 'assertion failed: res.eax == 0', /root/.cargo/registry/src/
sasi8985note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace10:43
sasi8985fatal runtime error: failed to initiate panic, error 510:43
lkclhi sasi8985 welcome10:44
lkclok, first thing, we only support debian/1010:44
openpowerbot[mattermost] <lkcl> for this exact reason11:01
lkclhowever there is slightly more to it11:02
lkclwhen doing ASICs you *absolutely cannot have* any possible differences in library routines or versions of software11:02
lkclor versions of hardware11:04
lkclproducing subtle differences in the Tape-out (layout)11:04
lkclstrictly speaking, two people should be able to run the exact same automated script11:04
lkcland compare the *bare metal hard drive contents* after running the Tape-out for 36 hours11:04
lkcland the contents of the *bare metal* drives should be exactly the same11:05
lkclthen you can safely and confidently know that the TEN MILLION DOLLARS you are going to spend on Foundry Masks are ok11:05
lkclso please follow the instructions and use debian schroots11:05
lkclsasi8985: here;a=summary11:05
lkclthere's some instructions here that you can follow step-by-step:11:06
lkclbasically, if it doesn't work on a particular OS, not being funny, it's your problem to fix11:06
lkclif however you use the standard development environment that we chose for the project in order for everyone to be able to produce the exact same output11:06
lkcl(which is an Industry-standard practice for ASIC development to do that)11:06
lkcl*then* we will kick into high gear and help get it sorted11:06
lkclso please can you use the standard dev scripts (install a debian chroot) and let us know ok?11:06
lkclsasi8985: make sense?11:07
lkclbtw you pasted a bit too much into the IRC client (generally this is not good practice)11:07
lkclyou were lucky it did not "kick" or "ban" you, automatically :011:07
lkclinstead of pasting dozens of lines, it's best to either send to the mailing list (as text, not images)11:07
lkclor to raise a bugreport (
lkclor use a pastebin somewhere (debian run one, ubuntu run one, there are plenty around)11:08
lkclthese will do perfectly fine -
lkclbut, really, the bugtracker is the place to report bugs.11:09
sasi8985lkcl: yes got it.. i will try those scripts and get back to you if there are issues11:09
lkclsasi8985: how much memory on your laptop btw?11:10
sasi89854 gb ram :-(11:10
lkcli have *64* GB of RAM (!!) i was veeery lucky to have it donated11:10
lkclok well if you can review the Charter and you can send me an ssh public key i can probably give you a remote shell login to the Raptor Engineering sponsored TALOS-II workstation11:11
sasi8985lkcl: i saw your youtube video of building soc where you got read and write speeds of 30 and 40 mbps...but i am getting 1 and 0.7 the ram reason11:11
lkclthat and if it's a slower processor, yes.  i have an NVMe SSD, it is 2500 mbytes/sec read speed (!!)11:12
lkcli actually have diff11:12
lkcliculty getting my head round how fast it is :)11:12
lkclif you're happy to abide by the charter, i'm happy to let you use the TALOS-II workstation, remotely.11:13
lkclalso... you might also be able to get a remote login to Oregon State University computers.11:13
lkclyou can ask Ganesan about that11:13
lkclthe FPGAs OSU have, woooow11:14
sasi8985lkcl: yes...i have used those computers but same speed11:14
lkclwell, the Raptor TALOS-II is almost no other users and has ridiculous amounts of RAM and cores11:14
sasi8985lkcl: okay..may be ganesan should comment regarding this11:15
lkcli run the Libre-SOC project, so i can give you permission to log in to our sponsored TALOS-II machine, as long as you review and are happy with our Charter11:16
lkclOSU you have to speak with them, and Ganesan, yes.11:16
sasi8985lkcl:yeah... i just now saw a sim.vcd file in one of the directories maybe near the instruction level signal vcd file11:18
lkclsasi8985: oh btw what were those other questions you had?11:18
lkcl./ --trace (something like that)11:18
lkclyou should be able to run ./ --help11:18
lkclthe only thing is: the VCD file produced by litex is "damaged", subtly11:19
lkclit's not litex's fault, it's verilator11:19
lkclso depending on the version of verilator you are using it *might* be fixed, now.11:19
lkclif not, then use this:11:19
lkclvcd2fst sim.vcd sim.fst11:20
lkclfst2vcd sim.fst sim_no_longer_borked.vcd11:20
lkclyou will find, magically, that gtkwave can now properly show you the trace signals :)11:20
lkclthe "borked" symptoms you're looking for are that you display a trace signal in gtkwave and it looks completely blank.11:21
lkcl*including* sys_clk.  which is clearly and obviously false, esp. if you inspect the VCD file manually11:21
sasi8985yes i will try that too....i want to use microwatt with system c as it has some inbuilt libraries of interconnects.,fifo's etc can i do that? i think library is matchlib11:23
lkclfor that, there's the #microwatt channel.11:24
lkclwhich toshywoshy has just successfully got the bridge to OPF mattermost up and running again11:24
lkclor, you can log in here11:24
lkclSystemC is proprietary: Libre-SOC absolutely cannot use it.11:25
lkclwe are under "Audit" conditions (NLnet Privacy and Enhanced Trust)11:25
lkclplus, the company, RED Semiconductor, is seeking VC Funding based on full transparency, for security reasons.11:26
sasi8985One more question is there any chance of developing system verilog testbench for this soc.11:26
sasi8985lkcl: okay got it...i can't use.11:26
lkcloh, you can use it for microwatt, no problem.  they don't have such limitations11:27
lkclsure you can develop a SV testbench if you like11:27
lkclSystem Verilog is now supported by yosys i believe11:27
sasi8985lkcl: yes there are almost done11:27
lkcl"a small subset is supported"11:28
lkclbut ahh, interesting11:28
lkclremember though, that we have literally thousands of testbenches already11:28
lkclin the case of the IEEE754 FPU it's *hundreds* of thousands of testbenchs.11:29
lkclreally not kidding, it takes a week to run them all11:29
lkclthey're all automated behind python unit tests11:29 it..for me it will take months then11:30
lkclyeahh you don't want to run those :)  or, you can on the TALOS-II workstation, no problem11:30
lkcl24 cores (!!)11:30
lkclhtop is very funny, it reports 72 processes :)11:30
lkclbut the non-IEEE754 ones, you should at least try running some of them11:31
lkcl1 sec11:31
* lkcl just finding some...11:31
lkclok any of these:11:32
lkcl;a=tree;f=src/openpower/decoder/isa;hb=HEAD11:32 will be quite short11:32
lkclthat tests the *simulator*11:33
sasi8985yeah sure i will try them11:33
lkclwe use it for bootstrap11:33
lkclwhen we know the simulator is correct, then we can compare against the HDL.11:34
lkclsingle-step mode11:34
lkclextract the register file (and some memory) and compare them11:34
lkcluse "nohup" btw. or output the console garbage to a file, ok? :)11:35
lkcla loooot of debug output is printed11:35
lkclfor co-simulating the hardware-vs-simulator, this is quite short:11:36
sasi8985i will have to try all these  only then it makes sense11:36
lkclyehyeh, no exactly.11:37
lkcllearning-is-doing.  wait.... doing-is-learning :)11:37
lkclhere's the actual unit tests, divided by pipeline11:38
lkcl(similar to the way v3.0B PDF spec is organised)11:38
* lkcl lunch for me, now :)11:39
sasi8985okay :)11:44
sasi8985Thanks for all the help and guidance...i am learning a lot from these11:44
openpowerbot[irc] <vpandya> Is there any example which show SVP64 textual assembly ?13:15
lkclvpandya: yes13:39
lkcl1 sec13:40
openpowerbot[irc] <lkcl> vpandya: there's some actual functional examples for MP313:41
openpowerbot[irc] <lkcl> i need to choose a better "separator" than the exact same one as comment ("#")13:41
openpowerbot[irc] <lkcl> here:;a=blob;f=media/audio/mp3/mp3_0_apply_window_float_basicsv.s;hb=HEAD13:42
openpowerbot[irc] <lkcl> there's actual functional Makefiles in there;a=tree;f=media/audio/mp3;hb=HEAD13:43
openpowerbot[irc] <lkcl> but use this one to "wget" the data:;a=blob;f=media/Makefile;hb=HEAD13:43
openpowerbot[irc] <lkcl> if you need more examples give me a shout.13:46
programmerjakesasl8985 did you get that error running in a VM? that particular error is caused by the x86 cpuid instruction reporting it supports getting some extended state, but not returning that extended state when asked again -- symptoms of a broken VM implementation. try using different virtualization software13:55
sasi8985programmerjake: Hi programmerjake. No i got that error from University of oregon system(Jupiter). some yosys assertion failure14:03
lkclahh you'll be on a Virtual Machine, that's why14:04
lkclthat needs to be reported to OSU, then14:04
sasi8985Sure i will tell Ganesan14:06
sasi8985lkcl: I have tried that unix "pipe" thing to issue commands through jtag ""14:10
lkclit worked!14:11
lkclyes, that command simply runs JTAG "idcode"14:11
programmerjakesasi8985 after a little more research turns out your cpu/vm is just fine, the cpuid crate just made an incorrect assumption which is violated by recent intel cpus that support avx512_bf1614:11
lkclTDO (000018ff)14:11
lkclthat's the JTAG idcode14:12
lkclso the next thing to try, if you like, is the *python*-based version of openocd "remotejtag"14:12
lkclwhich... 1 sec...14:12
sasi8985programmerjake: it is an open issue maybe i will just report it and try with working system14:13
programmerjakesasi8985 can you comment on that github issue with your /proc/cpuinfo? or you can email it to me and I can post it.14:15
programmerjakethis issue:
sasi8985programmerjake: yeah sure...shouild i send a log file of that14:16
lkclprogrammerjake: thx.  it's the oregon state university server14:16
programmerjakenah, it's cuz they have a recent intel cpu and the cpuid crate made an incorrect assumption about how the cpuid instruction works14:17
lkclwhat am i doing... oh yes, trying to find the test14:17
lkclsasi8985: here you go;a=tree;f=src/soc/debug/test;hb=HEAD14:18
lkcland there's this as well:;a=blob;f=src/soc/debug/;hb=HEAD14:18
lkclbear in mind, those are hoooorrribly slow14:18
lkcllike... 50-100 JTAG bits per second, something mad like that14:19
lkclalso: annoyingly, the JTAG "reset" command, when sent to verilator, goes and trashes the memory, resetting it back to running the BIOS.14:19
sasi8985lkcl: Okay...i will leave this system on for 4 hours and see atleast one command is passed14:20
lkclbut, at least you can show the JTAG wishbone read/write is working.  and JTAG stop/start14:20
lkclsasi8985: it shouldn't take anywhere near that long14:20
lkcllike... 3-4 minutes14:20
lkcljust not "3-4 seconds" like you'd normally expect14:20
programmerjakesasi8985 send your /proc/cpuinfo, only the assertion failed line is relevant to the cpuid crate14:21
sasi8985okay :)14:21
sasi8985programmerjake: thread '<unnamed>' panicked at 'assertion failed: res.eax == 0', /root/.cargo/registry/src/
lkclsasi8985, run "cat /proc/cpuinfo > {some_file}" or "cp /proc/cpuinfo {some_file}" on jupiter.14:24
lkcland drop it into pastebin14:24
lkclprogrammerjake: ^14:28
programmerjakethx, I'll post that to the github issue14:28
* lkcl ok, cool. off out for a walk. sitting down all day, getting antsy :)14:28
programmerjakesasi8985 posted to github:
sasi8985programmerjake: Thanks.14:34
programmerjakeyou'll just have to run it on a cpu that doesn't support avx512_bf16 for now, or figure out how to patch that cpuid crate (sounds like a pain)14:37
sasi8985programmerjake: yes...i will run it on other system14:48
programmerjakesasi8985 I also opened bug reports and
sasi8985great, thank you :)15:27
sasi8985_Regarding python based opencod i am getting "" i installed this "" but no luck.15:47
programmerjakeyou need python 3.7 or later:
sasi8985_okay Thanks15:53
lkclsasi8985_, please don't put quotes around the pastebin, it stops irc clients from being able to open the link, because they think the " at the end is part of the URL15:59
lkclyep, the default version of python from the chroot scripts comes out as python 3.715:59
sasi8985_Okay i will take care.16:00
lkclezcellent, the FFT "REMAP" triple generators work16:07
lkcl(sasi8985_ for context there, we're aiming to do the loops of Matrix Multiply, FFT and DCT, with a *single* instruction)16:15
lkclplus some context setup, but hey :)16:15 this for power isa also or only riscv16:17
programmerjakenot for riscv, we're working on only openpower for >1yr16:18
programmerjakethough I wouldn't object to their using our design :)16:18
sasi8985_okay..i thought for riscv as its there in riscv directory16:20
programmerjake?? where?16:20
programmerjakeah, we never got around to renaming the git repo. it is in the openpower directory in that git repo though16:22
lkclyes it's a bit of a pain, renaming that repository is a bit awkward16:22
lkcli have to symlink it to stop older links from breaking16:23
lkcland redo the ikiwiki configuration, and... ur....16:23
lkclthis is what FFT looks like in x86 assembler16:25
lkcl666 lines!16:26
lkclaltivec isn't much better - that's a *macro* there16:26
lkclslightly horrified to see that assembly macro might actually be recursive16:27
lkclwith the SVP64 FFT-REMAP schedule i think we'll be down to about 20-25 lines of assembler16:28
lkclfor *variable* length power-of-two FFT16:28
programmerjakegetting visions of turing complete macros using continuation-passing-style... :P16:28
sasi8985_is theer anything wrong with systems
lkclsasi8985_, don't use python 3.8 either17:16
lkcl*only* use python 3.717:16
lkclprogrammerjake: yeahno :)17:17
lkclit'd be hilarious, having a mini CPU inside a CPU17:17
lkclin all seriousness we have to be really careful about gate latency for REMAP17:17
lkclonly using adds and MUXes17:18
lkclthe FSM's going to be a bit of a pig to be honest17:19
sasi8985_lkcl: jtag sim stopped but some different bios is loaded this time as it has some different crc than previous one18:36
sasi8985_also if i want to run python codes on libresoc should i need to connect to fpga?18:48
lkclsasi8985_, yes, every single time that you run ./, the entire BIOS source code is recompiled.18:59
lkcla date and time stamp is inserted into the source code automatically.18:59
lkcltherefore you will never, under any circumstances, get the exact same CRC.19:00
sasi8985_lkcl: i think there is a deine for time and date19:00
lkclunless you modify the BIOS source code to remove the insertion of time/date19:00
lkclthis is "Not_Our_Problem(tm)" :)19:00
lkclit merely explains the anomalous, unexpected, behaviour19:00
lkclby "running some python codes", do you mean, "do you want to run micropython"?19:01
lkcl"some python codes" makes no sense19:01
lkcl(there is no such thing as "python codes")19:01
sasi8985_i meant like a helloworld program in python19:02
lkclthen you'll need to run micropython.19:03
lkclwhich can be done by using the binary from the tests directory in microwatt19:03
lkcland modifying (by hand) at this line:19:03
lkclobviously, take out the line "ram_name=None" that comes after it19:03
lkcli haven't run any of the microwatt binaries in a while19:04
* lkcl trying one now19:04
sasi8985_okay i will try to run that hello world.bin19:04
lkclok runs the BIOS...19:05
lkcljust bear in mind that the microwatt binaries assume a 16550 UART19:06
lkcllitex uart is *NOT* a 16550 UART.19:06
lkclhey, the hello_world.bin works.19:06
lkclso you won't be able to interact with micropython over the console19:07
lkclbecause although it will print at the console (the "write" of litex UART happens to coincide with 16550 UART write addresses)19:08
lkclthe reading (typing) does NOT19:08
lkclyou'd have to update the micropython source code in microwatt to use litex's way of doing UART.19:09
lkcl*then* it will work, ok19:09
sasi8985_yeah i am getting it19:09
lkclat least this works19:09
lkclMicroPython v1.12-571-g16d6cb7f7-dirty on 2020-06-23; bare-metal with POWERPC19:09
lkclType "help()" for more information.19:09
lkclbasically you have to develop three things, all at the same time:19:10
lkcl1) the software19:10
lkcl2) the peripherals19:10
lkcl3) the main core19:10
lkcl*all three absolutely have to match*19:10
lkclerrr i have no idea where that binary came from.19:10
lkclyou'll have to ask on the #microwatt channel19:11
lkclor on here19:11
lkclhmm looks like it was built externally and only the binary added19:12
sasi8985_for fpga also can i can make some changes in;a=blob;;h=18aca0eedf6f9f8ab3ecffa5fd6e98d305e92376;hb=HEAD and generate bitstream19:13
lkclif you happen to have access to an Arty A7-100 that would be _great_19:14
lkclbear in mind that although it says VERSA_ECP5 it also has a class for the Radeona ULX3S19:14
lkclwhich is a great board, very low cost19:14
lkclnote in that file, there is JTAG btw?19:15
lkclto test that, you need to get some sort of FT232 USB dongle19:15
sasi8985_OSU has xilinx zynq-7 mpsoc+ fpga i guess19:16
lkcland then (ta-daaa) you can connect it to the FPGA board and run the exact same as you did earlier against the simulation19:16
lkclwell, then, nmigen will have to be modified to support whatever-it-is.19:16 i think we should buy some low cost board and test it.19:18
lkclor, you export to verilog and you're on your own from that point onwards19:18
lkclbasically... yes.19:18
lkclGanesan is talking with Tim Pearson to get some of the ModBMC boards connected to Raptor TALOS-II workstations for you19:19
lkclyes libresoc.v19:19
lkclhowever you also need to set up peripherals etc. etc. etc. etc.19:19
lkcla core is just a core19:19
lkclit's no good if it has no memory, or anything else to connect to the outside world, is it?19:20
sasi8985_yes...i want to run programms from sdram and send the transactions through pcie19:20
lkclok then you need to investigate what type of internal Bus Architecure the zync-7 has19:21
lkcl(which is probably AXI-4 - we have everything set up to do wishbone because it's not patented and is a lot simpler)19:21
sasi8985_For this i thought i will write some basic assembly program and initialize main_ram of core with this program and generate some .vcd files19:21
lkclmicrowatt likewise uses wishbone19:22
lkclDDR RAM requires "training" initialisation.19:22
lkclbefore it can even *become* DDR RAM.19:22
sasi8985_cant we write like OUT a2 address19:23
lkclnnope.  not until you've run the "DDR training".19:23
lkclthis is a whooole area you need to investigate and learn about19:23
sasi8985_yes..i should19:24
lkclULX3S uses SDRAM (133mhz) precisely for this reason19:24
lkcla couple of other boards use HyperRAM19:24
lkclthe reason is because DDR runs so fast, you get impedance mis-match19:25
lkcland the A0-12 and D0-D31 signals *bounce back* and destroy the signals19:25
lkclto "fix" that, both the DRAM PHY *and the DDR IC* have built-in tunable RC circuits19:26
lkclyes, really19:26
lkcland the "training" basically goes through all possible permutations of the settings19:26
lkcl"does this work with controller RC-circuit timing = 0.1ps phase delay yes no"19:27
lkclok? ok try 0.2ps19:27
lkclno? ok try 0.3ps delay19:27
lkclit's completely insane but that's how you can get 800mhz, 1300 mhz, 2400 mhz, 3200 mhz etc. etc. etc.19:27
sasi8985_i dont know about these kind of circuits19:27
lkclRC: resistor-capacitor19:28
lkclno, and normally you wouldn't have to.19:28
lkclwelcome to low-level hardware19:28
lkclall of these circuits are *built-in* to the FPGAs and into DRAM ICs19:28
lkclso you don't have to "know" about them, but you *do* have to run some assembly code which initialises the interface.19:29
sasi8985_okay discharge and charge are the pulse widths? for speed19:29
lkcletc. etc.19:29
lkcland some other timings N-N-N whatever those are19:29
lkcla good BIOS will have support for these, already.19:30
sasi8985_okay i got it there is a gap for in interaction between ram and cpu19:32
sasi8985_i thought it like if we give clock to ddr ram controller it will automatically start transactions19:32
lkclSDRAM, yes.19:38
lkclDDR2, DDR3, DDR4, no19:38
lkclbecause SDRAM is only 100, 133 or 166mhz19:38
lkclso there is no signal-bounce at that kind of speed19:38
lkclor, there is...19:38
lkcl... but it quickly dies down and doesn't interfere with the next signal19:38
lkclDDR2: 400mhz clock rate19:38
lkclDDR3: 800mhz clock rate19:39
lkclDDR4: 1.6 ghz19:39
lkclthe speed of light is 3x10^819:39
lkclso 3 ghz is only... err... 10 cm?19:39
lkclso the signals start bouncing back and interfering with the next clock19:40
lkclsimple physics19:40
lkclever played with a slinky? :)19:40
lkcland had it "bounce" a wave back and forth?19:40
lkclwatch the signal "bounce back"19:42
lkclthat's *exactly* what happens on DDR signals...19:42
lkclyou have an "absorber" at the other end19:42
lkclperfectly matched to the "friction", to the length, to the weight of the slinky, to the speed of the waves19:43
lkcletc. etc. etc. etc.19:43
sasi8985_got it..19:45
sasi8985_For sdram speed is less and the signal bounce doesn't start or if starts ends quickly is this?19:46
sasi8985_its enough for me today. Good night.19:53

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