| lkcl | ha, irony, for assuming that qemu would have addg6s. sigh | 10:07 |
|---|---|---|
| richardwilbur[m] | Do we know what coverage qemu has of POWER ISA? | 19:04 |
| richardwilbur[m] | Could I implement say addg6s and test against POWER HW? | 19:06 |
| programmerjake | I'd assume qemu implements all the commonly used instructions... | 19:15 |
| mwielgus | hello | 19:16 |
| *** mwielgus is now known as mikolajw | 19:16 | |
| programmerjake | richard.wilbur yes, we have access to a Power9 server provided by Raptor, lkcl can give you a user account | 19:17 |
| programmerjake | mwielgus hi | 19:17 |
| programmerjake | richard.wilbur if you know Rust, modify power-instruction-analyzer to add addg6s, cbcdtd, and cdtbcd. | 19:22 |
| programmerjake | for an example, see https://git.libre-soc.org/?p=power-instruction-analyzer.git;a=commitdiff;h=de665083a9d36e6ed82890c23272c3c7c046ccbe;hp=50cab0eace9512917b46538ec2ee3fec350dc3a0 | 19:22 |
| programmerjake | if you don't know/want to learn Rust, then you can probably find/write a different program for testing addg6s | 19:24 |
| programmerjake | power-instruction-analyzer is a combined OpenPower instruction tester and reference implementation with Rust models for each instruction that can be called from Python | 19:29 |
| programmerjake | allowing you to write the reference implementation and then develop the hardware to match it allowing development on a non-Power cpu (e.g. I do my development on x86-64). | 19:31 |
| programmerjake | that's what we used to figure out the exact behavior of Power9 for the div/mod instructions, which aren't completely specified by the OpenPower spec | 19:32 |
| richardwilbur[m] | My dev env. is also presently x86-64. | 19:34 |
| richardwilbur[m] | I have nothing against learning Rust but expect to need both a good reference and probably some hand holding along the way. I expect there’s example code for several other instructions. | 19:34 |
| programmerjake | yes, lots of example code... | 19:34 |
| richardwilbur[m] | Are we running a source build of qemu or distro package? | 19:35 |
| programmerjake | you probably won't need to learn much Rust since addg6s, etc. are pretty simple | 19:35 |
| programmerjake | idk, I just use qemu from debian (though I think I use a more recent version) | 19:36 |
| mikolajw | I'm interested in helping you with your project. I currently work as a hardware verification engineer in a company that designs silicon cores (basically I just do measurements and process the data). I'm also a developer of KiCad. I can currently contribute about 5 hours per week to the project, but this is likely to increase significantly in this year. | 19:37 |
| programmerjake | mikolajw welcome! introduce yourself on the mailing list https://lists.libre-soc.org/mailman/listinfo/libre-soc-dev | 19:39 |
| richardwilbur[m] | That’s good for the speed of implementing this but disappointing from the perspective of trying to learn a new language. Enough to whet my appetite, I suppose. | 19:39 |
| programmerjake | well, the parts of Rust you'll likely need for this aren't really the parts where Rust stands out from all the other programming languages | 19:40 |
| programmerjake | install rust via https://rustup.rs/ | 19:41 |
| programmerjake | you'll need a nightly version since inline assembly has not been stabilized yet | 19:41 |
| programmerjake | a significant way rust differs from C for bit-manipulation is the `!` operator means bitwise-not for integers -- Rust doesn't need to disambiguate `~` vs. `!` since it has a separate bool type | 19:44 |
| programmerjake | you'll want to use the `overflowing_add` and/or `wrapping_add` methods: https://doc.rust-lang.org/std/primitive.u64.html#method.overflowing_add | 19:46 |
| programmerjake | https://doc.rust-lang.org/std/primitive.u64.html#method.wrapping_add | 19:46 |
| programmerjake | let me know if you need help, or you can ask on the rust users forum (they're very friendly): https://users.rust-lang.org/ | 19:54 |
| programmerjake | to run the native instruction tests, run gen-output.sh | 19:59 |
| programmerjake | it'll create a json file with all inputs/outputs and will output `model_mismatch` fields where they don't match | 20:01 |
| richardwilbur[m] | Thanks for the pointers. I’ve almost got my wife’s laptop back together. Had to mostly disassemble it to replace the DC Power input daughter card (on which the broken power jack was soldered). | 20:03 |
| programmerjake | fun... | 20:04 |
| programmerjake | I had to fix a laptop where the dc power input jack broke off the mobo, soldered a jumper across the cracked mobo | 20:04 |
| programmerjake | it only sorta worked | 20:05 |
| richardwilbur[m] | My youngest brother and his family are stopping by this afternoon and staying the night. So I’ll be preoccupied till tomorrow after they leave. | 20:06 |
| programmerjake | ok, have fun! | 20:06 |
| lkcl | mikolajw, hi, welcome, fantastic to hear | 20:18 |
| lkcl | if you know kicad, you're almost certainly also know gate-level design, which is hugely useful in this project. do you know python as well? | 20:19 |
| lkcl | if not, there's a series of gate diagrams on the wiki which need converting to SVG - veera is currently doing some of them | 20:23 |
| lkcl | there's all sorts of small things that need doing | 20:24 |
| mikolajw | lkcl: yes, I use Python everyday | 20:41 |
| lkcl | mikolajw, ah fantastic, because the HDL - and all the unit tests - are in python | 20:48 |
| lkcl | yes, really: HDL in python. we use something called nmigen (has its own IRC channel here on libera.chat) | 20:49 |
| mikolajw | yes, that sounds cool. In fact that was what exactly piqued my interest to this project when I read about it on Wikipedia for the first time | 20:50 |
| lkcl | nice | 20:51 |
| lkcl | you'll like this: i learned recently that the nmigen HDL gate-level simulator actually translates the Abstract Syntax Tree into a python program, in ASCII... | 20:52 |
| lkcl | then hands it to exec() and then compile()! | 20:52 |
| lkcl | you end up with an in-memory function which can be called to execute the combinatorial logic circuit :) | 20:52 |
| lkcl | i mean, i've done that sort of thing myself before, for expression evaluation in a website, but... dang | 20:53 |
| mikolajw | so a computer simulation can be performed easily as I understand | 20:56 |
| lkcl | yes. | 20:58 |
| mikolajw | when I was a university student I had a HDL class (Verilog) during which we wrote a VGA driver (from instructions) and then students had to make their own video games in Verilog (not from instructions) | 20:58 |
| lkcl | if you're used to circuits (and thinking about how to test them) then that's basically what it helps with | 20:58 |
| lkcl | nice | 20:58 |
| mikolajw | we used Vivado. One of the more unpleasant parts was that the final part of the implementation (I don't remember the terminology, I mean the part where you turn it into an actual FPGA program) took a significant amount of time | 20:59 |
| mikolajw | "FPGA program" | 20:59 |
| lkcl | well it's a lot simpler to think about in terms of classes and objects than it is to think in a programming language designed in the early 90s, which has reminiscent hints of BASIC and PASCAL... :) | 20:59 |
| lkcl | yyeah, well, compiling libre-soc for an ECP5 (using yosys and nextpnr-ecp5) still takes... mmm.... 8-10 minutes? | 21:00 |
| lkcl | it's not "short" but it's not completely mad, either | 21:00 |
| lkcl | do you have an FPGA board at all? | 21:00 |
| mikolajw | I don't anymore | 21:00 |
| mikolajw | but I can buy | 21:00 |
| mikolajw | but you said it is turned into an actual Python program -- can this be done to speed up testing? | 21:01 |
| programmerjake | well, when I had a similar project for a digital design class, I built a RV32I cpu: https://github.com/programmerjake/rv32 | 21:01 |
| lkcl | yes, definitely | 21:01 |
| lkcl | i love how that only took you what... 2 weeks? | 21:02 |
| lkcl | ok by "speed up", this is relative :) | 21:02 |
| lkcl | we actually only execute about 3-6 instructions per unit test, some even less than that | 21:02 |
| lkcl | it's just that there's hundreds (thousands) of them | 21:03 |
| lkcl | we need a test for add, a test for addi, a test for cmp, a test for cmpl, a test for cmpi, a test for bc, ld, lw, lwz, popcnt, etc. etc. etc. etc. | 21:03 |
| lkcl | it's actually very boring :) | 21:04 |
| lkcl | but, it's essential work | 21:04 |
| lkcl | and creates a solid foundation, you know what i mean | 21:04 |
| lkcl | if you're interested in learning nmigen, here's some starting points: https://nmigen.info/nmigen/latest/tutorial.html | 21:05 |
| lkcl | robert baruch's one is one of the best | 21:05 |
| lkcl | please do install from latest git, don't use 'pip install nmigen', though. | 21:06 |
| lkcl | if you want to be lazy but also install the libre-soc HDL, use this | 21:06 |
| lkcl | https://libre-soc.org/HDL_workflow/devscripts/ | 21:06 |
| lkcl | you will end up with all the dependencies | 21:07 |
| lkcl | programmerjake: i did a comparative video of SVP64 Vertical-First and Horizontal-First Mode for you, i've got to upload it. | 21:08 |
| lkcl | as i was going through it i realised it still needs thought | 21:08 |
| programmerjake | neat! | 21:09 |
| lkcl | cesar: nicely done with the ldst exceptions | 21:10 |
| lkcl | tobias is fixing some things with dcbz as well | 21:10 |
| programmerjake | I'm pretty sure I understand them...sorta like you understand how a compiler works but it is still more complex/confusing than table lookup | 21:11 |
| mikolajw | ok, I'll play with the toolchain and hopefully I'll be able to contribute within the following weeks | 21:12 |
| programmerjake | the video will probably be useful for others too | 21:12 |
| lkcl | mikolajw, cool. one thing i recommend doing: | 21:12 |
| lkcl | * get nmigen to compile to verilog (or ilang) | 21:12 |
| lkcl | * run yosys | 21:12 |
| lkcl | * type "read_verilog {file.v}" or "read_ilang {file.il}" | 21:12 |
| lkcl | then type "show top" | 21:13 |
| lkcl | or "show {press tab twice}" and select a module (one of which _should_ be named "top") | 21:13 |
| lkcl | you need graphviz and xdot installed for that to work btw | 21:13 |
| lkcl | what you get is a *graphical 2D* gate-level representation of the HDL | 21:13 |
| lkcl | i was LITERALLY incapable of understanding nmigen HDL without seeing the gate-level design | 21:14 |
| lkcl | i had to run "show top" after every single edit, for about 2-3 months. | 21:14 |
| lkcl | after 6 months i didn't need to do it any more, but until i had that "brain understanding" of the link between the HDL and the logic connections, i was wasting my time! | 21:15 |
| lkcl | some people can make the connection instantly, others can't [couldn't, including me]. | 21:16 |
| mikolajw | do you refer to Nmigen HDL specifically or HDL in general? | 21:16 |
| lkcl | if you're struggling with nmigen, because you've used KiCAD, you may find "show top" to be really useful | 21:16 |
| lkcl | well, actually, yes, it could well be | 21:16 |
| lkcl | but surprisingly, i find verilog to be readable. i don't _like_ it, but it's readable :) | 21:17 |
| lkcl | nmigen on the other hand, i just couldn't mentally cross-associate the python code with the gates | 21:17 |
| lkcl | and i've been using python since 1999/2000 :) | 21:17 |
| programmerjake | I am one of the make-the-connection-instantly people, maybe because of my experience with writing compilers? | 21:18 |
| lkcl | yehyeh, if you're used to ASTs that makes a lot of sense | 21:18 |
| lkcl | richardwilbur[m], jn, klys, lxo meeting! | 23:31 |
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