Saturday, 2021-09-11

Veera[m]Hi luke04:10
Veera[m]little help with pip04:10
Veera[m]what does it mean by running pip -r requirements.txt04:10
Veera[m]and requirements.txt has a line like:04:10
Veera[m]-e third_party/migen04:11
lkclit means, "go get those packages named in the requirements.txt file"11:32
lkcl1 sec...11:33
lkclman pip311:33
lkclapparently it *uninstalls* those packages (!!)11:33
lkclah no11:34
lkclthat's if you use the uninstall command11:34
Veera[m]I am using pip3 install -e thirdparty/migen11:35
lkclit's the equivalent of "python3 develop" for that specific package11:35
Veera[m]read manual page. it says runs the program from source directory itself. Does not installs into /usr/lib/python??11:36
lkclthe way that "python3 develop" works is:11:37
lkcl1) there **IS** a "package-indicator" installed into /usr/lib/python11:37
lkcl(or other location)11:37
lkcl(which might be ~/.env/blahblah if you are using venv)11:37
lkcl(which might be /usr/local/lib/pythonN.N/dist-packages)11:38
lkclbut that "indicator" - a .pth file - points ***BACK*** to the ***LOCAL*** actual source code11:38
Las[m]lkcl: Is there any documentation for targeting an FPGA?13:40
lkclLas[m], it's 2 commands, listed in the README of libresoc-litex.15:34
lkcl1 builds15:34
lkcl2 uploads15:34
lkcl1 sec15:34
Las[m]lkcl: Thanks. Can you explain the relation between this repository and the soc repository?15:39
Las[m]So I assume you're supposed to use this repository if you want to target an FPGA?15:39
Las[m]And if it's for real hardware, you use experiments9?15:39
lkclthere's effectively none.  or: one uses the output of the other15:39
lkclexperiments9 is purely the "instructions to coriolis2 on what it should do to take the HDL for the ASIC and turn it into GDS-II files for that ASIC"15:40
lkclthe libresoc-litex repository leverages litex to create peripherals and connect them to a core.15:41
lkclthat's litex's "job"15:41
lkcllitex is capable of 3 different "jobs"15:42
lkcl1) simulations15:42
lkcl2) creating HDL suitable for uploading to FPGAs15:42
lkcl3) after a **LOT** of pissing about, creating HDL suitable for use in ASICs15:42
Las[m]Is litex a standard tool or Libre-SoC-specific?15:42
lkclit's a tool that's created by an individual known as "Florent Kermacc" who has caused us a LOT of headaches, including making unfounded complaints about us to the OpenPOWER Foundation.15:43
lkclthose complaints were terminated with prejudice after we explained the inappropriateness of Florent's complaints15:44
lkclanswering your question: litex is a tool.15:44
lkclit's not maintained by us. we simply use it.15:45
lkcland won't be in the future (due to Florent's seriously problematic behaviour)15:45
Las[m]So looking at, I can see a `.il` file is output, is this what's used in the `libresoc-litex` repository?15:45
lkcllitex only accepts verilog as input15:46
lkcltherefore, we had to undergo a series of conversions15:46
lkcl(which yosys handles... mostly perfectly)15:46
lkclwe found however that the conversion process didn't quite work for SRAM (memory) cells, so converted over to verilog.15:47
lkclJean-Paul however very kindly adapted coriolis2 to accept ".il" files, but due to the issues with yosys conversion we stopped using it.15:47
lkclhence, outputs verilog, not ilang.15:48
Las[m]So ilang is also a HDL?15:48
lkclit's yosys's "internal" representation15:49
lkclILANG aka RTLIL15:50
lkclit's capable of supporting all concepts of other HDL languages, and consequently is the "intermediary".15:50
lkcla bit like how Esperanto is often used by automated language translators because it is "simpler" and has a regular grammar15:51
lkclyou'll see there are "read_ilang" and "write_ilang" commands15:52
lkclas well as "read_verilog" and "write_verilog".15:52
Las[m]So you're saying you stopped using the `.il` files, will you begin using them after you drop litex?15:52
lkclif you install the yosys-ghdl plugin, you get a "read_vhdl" command as well15:52
lkclstopped using the il files... as part of the process of converting to GDS-II files, yes.15:53
lkclstopped using .il files entirely.... no15:53
Las[m]What are the GDS-II files again?15:53
Las[m]I've seen them mentioned before15:54
lkclGDS-II files are the artwork (bitmap-like) for the layers in an ASIC.15:54
Las[m]It might not be very relevant for what I'm doing so just a quick description might be fine15:54
lkclyou have METAL layers15:54
Las[m]Ah, makes sense15:54
lkclyou have... N-layers15:54
lkcland etc. etc.15:54
lkclwhich are different chemical compounds15:54
lkclapply them in what is effectively and literally a 3D printing process (literally like 3D printing "slices") and you build up an ASIC15:55
Las[m]What is the file extension for GDS-II files?15:55
lkcl-rw-r--r-- 1 lkcl lkcl     22769 Sep  6 21:44 chip_r.spi15:55
lkcl-rw-r--r-- 1 lkcl lkcl    295404 Sep  6 21:44 chip_r.ap15:55
lkcl-rw-r--r-- 1 lkcl lkcl 360803640 Sep  6 21:44 chip_r.gds15:55
Las[m]I noticed you have some prebuilt GDS-II files15:56
lkclyes, that's accurate, btw: 360 MEGABYTE output15:56
Las[m]like "libresoc_logo.gds"15:56
Las[m]Is this a physical logo, not a circuit, that's meant to be visible on the chip?15:56
lkclyes, there exist GDS editors and also python programs around that can convert PNGs to GDS-II15:56
Las[m]Thanks, there's honestly quite a lot of build steps I need to understand for this IMO15:57
Las[m]So is the `libresoc-litex` repository used at all when targeting an ASIC?15:57
lkclyep, there are.  this is just how it is15:57
lkclyes it is.15:57
lkclit's triple-purpose15:57
lkcl1) - simulations15:58
lkcl2) - ECP5 FPGA15:58
lkcl3) - ASIC15:58
Las[m]Makes sense, matches the three uses of litex15:58
lkclbear in mind, litex *doesn't* support ASICs out-of-the-box.15:58
lkclit's down to the IO pads.15:59
Las[m]Which is why you have libresoc-litex I assume?15:59
lkclin a simulation, the IO pads are just some code. all great.15:59
lkclin an FPGA, it's the *FPGA* that handles the IO - and you can have either input, output, or bi-directional16:00
lkclFPGA input you get one wire16:00
lkclFPGA output you get one wire (an output)16:00
lkclFPGA bi-directional you need 3 wires (in, out, output-enable) but they're handled by the FPGA toolchain16:00
lkclthere's classes in litex which take care of that for you16:00
lkclbut for an ASIC, you actually have to output - from your HDL - the *three* signals, explicitly, per IO pad16:01
lkclgiven that litex IO peripherals weren't designed to cope with that scenario, i had to cut/paste copy a whole bunch of peripherals and modify them.16:01
lkclFlorent pissed me off by refusing to accept patches except via use of a github account.16:02
lkclthere's a lot more to it, but... yeah.16:03
Las[m]I assume it's ?16:03
lkclthe code he wrote actually saves a huge amount of time.16:04
Las[m]How does `make -C src/soc/litex/florent ls180` tie into this?16:04
lkclit's an accumulation of 15 years of expertise.16:04
Las[m]In the `soc` repository, after you've run `` or whatever it was called16:04
lkcl1 sec16:04
lkclwhere did you see that?16:05
Las[m]It's also in the Makefile16:05
lkcli made libresoc-litex a git submodule of soc, for convenience.16:05
Las[m]I didn't notice16:06
Las[m]I haven't initialized the submodules16:06
lkclotherwise they could get out-of-sync16:06
lkclit should have been the other way round16:06
lkclor better16:06
lkcla "top-level-everything" repo with *only* submodules in it16:07
Las[m]If you want to reproducibly link together different versions of software, Nix is the perfect tool for that FYI16:07
Las[m]specifically, specific versions of software16:08
lkcldoes nix allow builds to be edited?16:09
lkcli.e. once installed can they be edited?16:09
lkcland for development to take place "as usual"... but just with "specific versions"?16:09
lkcli doubt very much that it does (because it's designed, duh, to deliver specific versions)16:10
lkclwhich makes it wholly unsuited for use as an active development tool...16:11
lkcl... but great for delivering specific versions of tools... *that you use but have no intention of editing*16:11
lkclwe need that combination: specific versions... *and* the ability to work seamlessly with *edited* variants of those specific versions16:12
lkclaka "python develop" mode16:12
* lkcl afk16:13
Las[m]Yeah if you're editing them in tandem, submodules are better16:14
Las[m]BTW, what is missing for ?16:20
justinrestivo[m]<lkcl> "and for development to take..." <- this is precisely how I use it at work, now that submodule support has been added.19:30
justinrestivo[m]* at work and personal projects, now19:31
justinrestivo[m]s/at work//19:32
justinrestivo[m]I'm not sure I would describe it as "seamless" yet, but it's worked well enough19:34
justinrestivo[m]Before submodule support was added it was a lot more strained. I would have scripts that repeatedly updated lockfiles before building. Definitely not as nice from a usability standpoint.19:35
justinrestivo[m]s/worked/leaps/, s/well/and/, s/enough/bounds better than before/19:36

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