Monday, 2021-10-11

lkclcan't remember10:20
lkclghostmansd, changing EXTS is off the table, it's too low-level a function with way too high a dependency on its existing behaviour10:21
* lkcl only just starting to wake up10:21
Veeralkcl: Hi13:59
Veeralkcl: what is the status of Symbiflow (Bug 654)?14:00
cesarI think I found a DMI test case, including single-step, on;a=blob;;h=550339e46a22169fe19510da5d3032202f3f8aec;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a#l18614:14
cesarI'll try to run it.14:14
ghostmansd[m]lkcl: yep, that's what I meant, sorry for confusion. I remember we end up adding another function. :-)15:59
*** Awoobis is now known as `Awoobis`19:22
lkclVeera[m], as in the bugreport.19:26
lkclthe exact same error (capnp related) occurred19:26
lkclso that needs triaging19:27
lkclcesar, yes that's a good one.  the FSM is a pig.19:27
lkclbut functional19:27
lkclinstalling litex, you have to get the exact versions of the litex submodules right. and patch it19:28
*** `Awoobis` is now known as Awoobis19:40
cesarIt's booting the LiteX BIOS!19:45
cesarVerilator sure is fast to compile, compared to cxxrtl...19:46
cesarGot: /home/cstrauss/src/litex/litex/build/sim/core/sim.c:95 Could not find module jtagremote19:48
cesarIt didn't build the jtagremote module for some reason. Investigating.19:49
cesarHad to manually add it to litex/build/sim/core/modules/Makefile...20:08
cesarWell, by simply running ./, I do get to the LiteX BIOS.20:14
cesarBut, with ./ --debug --variant=standard, I get20:14
cesar%Error: /home/cstrauss/src/soc/src/soc/litex/florent/build/sim/gateware/sim.v:8167: Pin not found: dmi_addr_i20:15
cesar%Error: /home/cstrauss/src/soc/src/soc/litex/florent/build/sim/gateware/sim.v:8168: Pin not found: dmi_din20:15
cesar... etc.20:15
lkclyes that's it, add jtagremote to the Makefile21:04
lkclah that means you compiled with the wrong options to issuer_verilog.py21:04
lkcl1 sec21:04
cesar--debug dmi?21:05
lkclyyyyeah that sounds right21:05
lkcl--debug=dmi _should_ be the default21:05
lkclyou might have compiled previously for ls18021:05
lkcl(which takes --debug=jtag)21:06
cesar... at least I got to try the openocd command line (and it worked!)21:06
lkcloooo :)21:07
lkclyou _should_ also be able to run the command21:07
lkclwhen the reset is run, because the BIOS is a ROM, it trashes the memory contents you uploaded21:07
lkcland starts the BIOS again from the beginning21:07
lkclbut at least you can stop, wishbone-write-then-read21:08
lkcla slightly different procedure would be21:08
lkclbut yes, openocd being able to read the Manufacture ID is a really good sign21:09
lkclnow all we need is a powerpc target that understands the JTAG/DMI format/registers21:09
lkclwhich doesn't exist - at all - in openocd21:10
lkclthere's plenty of ARM targets.21:10
lkcland an OR1k target21:10
lkcland some MIPS targets21:10
lkclbut absolutely no powerpc targets of any kind21:10
lkclbecause IBM POWER8/9/10 all use FSI, so why would you need openocd again?21:10
lkclsigh :)21:11
cesarUrjtag is a software like openocd. It has support to many cables, can send SVF files, etc.21:15
cesarSomeone patched Urjtag to have a Python interface.21:15
cesarSo you could have a DMI to JTAG converter in Python, and have Urjtag send it.21:16
lkclcesar, it's such a simple protocol (jtagremote) that i wrote an adapter in python21:18
lkclJTAGServer and JTAGClient21:19
lkclthey work back-to-back, together21:19
lkclso you can actually connect openocd with jtagremote... *to test_issuer*! :)21:20
cesarCan openocd serve jtagremote, when you already have a cable?21:20
lkclit can act as a gateway21:20
lkcland i just copied that (in python), created a similar client/server21:21
lkclof course it's brain-dead simple, uses select() single-process21:21
lkclso you can only have one connection at a time, but duh, you can only have one connection at a time anyway21:22
cesarSo, do we already have a DMI to jtagremote adapter?21:22
lkclit's also horribly slow because it's running within nmigen sim and does socket select/read21:22
lkclDMI-to-jtagremote... no21:22
lkclwe have JTAG-to-DMI21:22
lkcland jtagremote-to-JTAG21:22
lkclat which point you can either:21:23
lkclconnect with openocd or21:23
lkclconnect with JTAGClient (which is what and the other unit tests do)21:23
lkcloh look it appears i did actually write a DMI simulation as one of the unit tests21:24
lkclif urjtag supports SVF file it *should* just work21:25
lkclbut then again, so does openocd21:25
lkcland i would not imagine it would be too hard to adapt Chips4Makers[m] c4m-jtag SVF unit tests to run over jtagremote (create a socket, send stuff) either21:26
lkcltoshywoshy, just noticed mattermost bridge stopped working wednesday for #libre-soc!  fine to oftc.net21:27
cesarI guess we could replace the DMI unit test in (the pig-like FSM) by a true Python test, using JTAGClient to send start/stop/step commands over JTAG/DMI.21:34
cesarRegenerated the verilog with --debug=dmi, and got to see the debug output from the DMI FSM test in Will examine the output, to see if it makes sense.23:43

Generated by 2.17.1 by Marius Gedminas - find it at!