| lkcl | can't remember | 10:20 |
|---|---|---|
| lkcl | ghostmansd, changing EXTS is off the table, it's too low-level a function with way too high a dependency on its existing behaviour | 10:21 |
| * lkcl only just starting to wake up | 10:21 | |
| Veera | lkcl: Hi | 13:59 |
| Veera | lkcl: what is the status of Symbiflow (Bug 654)? | 14:00 |
| cesar | Regarding https://libre-soc.org/irclog/%23libre-soc.2021-10-10.log.html#t2021-10-10T16:08:12 | 14:14 |
| cesar | I think I found a DMI test case, including single-step, on https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;h=550339e46a22169fe19510da5d3032202f3f8aec;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a#l186 | 14:14 |
| cesar | I'll try to run it. | 14:14 |
| ghostmansd[m] | lkcl: yep, that's what I meant, sorry for confusion. I remember we end up adding another function. :-) | 15:59 |
| *** Awoobis is now known as `Awoobis` | 19:22 | |
| lkcl | Veera[m], as in the bugreport. | 19:26 |
| lkcl | the exact same error (capnp related) occurred | 19:26 |
| lkcl | so that needs triaging | 19:27 |
| lkcl | cesar, yes that's a good one. the FSM is a pig. | 19:27 |
| lkcl | but functional | 19:27 |
| lkcl | installing litex, you have to get the exact versions of the litex submodules right. and patch it | 19:28 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=700 | 19:29 |
| lkcl | https://libre-soc.org/HDL_workflow/litex_ls180/ | 19:29 |
| *** `Awoobis` is now known as Awoobis | 19:40 | |
| cesar | It's booting the LiteX BIOS! | 19:45 |
| cesar | Verilator sure is fast to compile, compared to cxxrtl... | 19:46 |
| cesar | Got: /home/cstrauss/src/litex/litex/build/sim/core/sim.c:95 Could not find module jtagremote | 19:48 |
| cesar | It didn't build the jtagremote module for some reason. Investigating. | 19:49 |
| cesar | Had to manually add it to litex/build/sim/core/modules/Makefile... | 20:08 |
| cesar | Well, by simply running ./sim.py, I do get to the LiteX BIOS. | 20:14 |
| cesar | But, with ./sim.py --debug --variant=standard, I get | 20:14 |
| cesar | %Error: /home/cstrauss/src/soc/src/soc/litex/florent/build/sim/gateware/sim.v:8167: Pin not found: dmi_addr_i | 20:15 |
| cesar | %Error: /home/cstrauss/src/soc/src/soc/litex/florent/build/sim/gateware/sim.v:8168: Pin not found: dmi_din | 20:15 |
| cesar | ... etc. | 20:15 |
| cesar | Investigating. | 20:15 |
| lkcl | yes that's it, add jtagremote to the Makefile | 21:04 |
| lkcl | ah that means you compiled with the wrong options to issuer_verilog.py | 21:04 |
| lkcl | 1 sec | 21:04 |
| cesar | --debug dmi? | 21:05 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=Makefile;h=3d4ea62db5a779f896d1f59665014783681f0523;hb=dd84c610a68a556eb532cee133df68c4354dbf32#l28 | 21:05 |
| lkcl | yyyyeah that sounds right | 21:05 |
| lkcl | --debug=dmi _should_ be the default | 21:05 |
| lkcl | you might have compiled previously for ls180 | 21:05 |
| lkcl | (which takes --debug=jtag) | 21:06 |
| cesar | ... at least I got to try the openocd command line (and it worked!) | 21:06 |
| lkcl | oooo :) | 21:07 |
| lkcl | you _should_ also be able to run the firmware_upload.py command | 21:07 |
| lkcl | but | 21:07 |
| lkcl | sigh | 21:07 |
| lkcl | when the reset is run, because the BIOS is a ROM, it trashes the memory contents you uploaded | 21:07 |
| lkcl | and starts the BIOS again from the beginning | 21:07 |
| lkcl | wark-wark | 21:07 |
| lkcl | but at least you can stop, wishbone-write-then-read | 21:08 |
| lkcl | a slightly different procedure would be | 21:08 |
| lkcl | stop | 21:08 |
| lkcl | reset | 21:08 |
| lkcl | wishbone-write | 21:08 |
| lkcl | start | 21:08 |
| lkcl | but yes, openocd being able to read the Manufacture ID is a really good sign | 21:09 |
| lkcl | now all we need is a powerpc target that understands the JTAG/DMI format/registers | 21:09 |
| lkcl | which doesn't exist - at all - in openocd | 21:10 |
| lkcl | there's plenty of ARM targets. | 21:10 |
| lkcl | and an OR1k target | 21:10 |
| lkcl | and some MIPS targets | 21:10 |
| lkcl | but absolutely no powerpc targets of any kind | 21:10 |
| lkcl | because IBM POWER8/9/10 all use FSI, so why would you need openocd again? | 21:10 |
| lkcl | sigh :) | 21:11 |
| cesar | Urjtag is a software like openocd. It has support to many cables, can send SVF files, etc. | 21:15 |
| cesar | Someone patched Urjtag to have a Python interface. | 21:15 |
| cesar | So you could have a DMI to JTAG converter in Python, and have Urjtag send it. | 21:16 |
| lkcl | cesar, it's such a simple protocol (jtagremote) that i wrote an adapter in python | 21:18 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtagutils.py;hb=HEAD | 21:19 |
| lkcl | JTAGServer and JTAGClient | 21:19 |
| lkcl | they work back-to-back, together | 21:19 |
| lkcl | so you can actually connect openocd with jtagremote... *to test_issuer*! :) | 21:20 |
| cesar | Can openocd serve jtagremote, when you already have a cable? | 21:20 |
| lkcl | yes | 21:20 |
| cesar | ! | 21:20 |
| lkcl | it can act as a gateway | 21:20 |
| lkcl | and i just copied that (in python), created a similar client/server | 21:21 |
| lkcl | of course it's brain-dead simple, uses select() single-process | 21:21 |
| lkcl | so you can only have one connection at a time, but duh, you can only have one connection at a time anyway | 21:22 |
| cesar | So, do we already have a DMI to jtagremote adapter? | 21:22 |
| lkcl | it's also horribly slow because it's running within nmigen sim and does socket select/read | 21:22 |
| lkcl | DMI-to-jtagremote... no | 21:22 |
| lkcl | ok | 21:22 |
| lkcl | we have JTAG-to-DMI | 21:22 |
| lkcl | and jtagremote-to-JTAG | 21:22 |
| lkcl | at which point you can either: | 21:23 |
| lkcl | connect with openocd or | 21:23 |
| lkcl | connect with JTAGClient (which is what firmware_upload.py and the other unit tests do) | 21:23 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/debug/test;h=d02755919edef4b0ecf1d962f522ae22152f2ac6;hb=HEAD | 21:23 |
| lkcl | oh look it appears i did actually write a DMI simulation as one of the unit tests | 21:24 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/dmi_sim.py;h=aa6760f484ee06dff9bd8b8a6b6b46a0c0353c2a;hb=HEAD | 21:24 |
| lkcl | if urjtag supports SVF file it *should* just work | 21:25 |
| lkcl | but then again, so does openocd | 21:25 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/openocd_test.sh;h=a18076669cafa1849676bf76eba936d0e8f47398;hb=HEAD | 21:25 |
| lkcl | and i would not imagine it would be too hard to adapt Chips4Makers[m] c4m-jtag SVF unit tests to run over jtagremote (create a socket, send stuff) either | 21:26 |
| lkcl | toshywoshy, just noticed mattermost bridge stopped working wednesday for #libre-soc! fine to oftc.net | 21:27 |
| cesar | I guess we could replace the DMI unit test in sim.py (the pig-like FSM) by a true Python test, using JTAGClient to send start/stop/step commands over JTAG/DMI. | 21:34 |
| cesar | Regenerated the verilog with --debug=dmi, and got to see the debug output from the DMI FSM test in sim.py. Will examine the output, to see if it makes sense. | 23:43 |
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