Saturday, 2021-10-30

tplatenI'm currently adding DCBZ support to src/soc/experiment/compldst_multi.py09:15
tplatenThe line comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn) seems unclear to me09:16
tplatenalso slg is 2 bits, the other signals are 3 bits09:16
tplatenslg = Cat(op_is_z, op_is_imm)09:16
lkcltplaten, be very careful, it is one of the most extreme complex FSMs in the entire design10:21
lkclit would be better if you didn't touch it at all, or, at least, added DCBZ by inputting zero as the immediate data from the outside10:22
tplatenI agree, so the input would be OP_ST for dcbz?10:22
tplatenif yes, I can undo my changes10:23
lkclwell, that's one thing that might be ok to do - let it have OP_ST/OP_DCBZ as the input option10:23
lkcloh wait i already have op_is_dcbz10:23
lkclor, you added it already10:24
lkclop_is_st can be set if op == OP_ST *or* op == OP_DCBZ10:25
tplatenSo I dont need op_is_st_or_dcbz10:25
* lkcl thinks10:25
tplatenhere's the most critical commit:;a=commitdiff;h=b322acae923be19bc382cec4092d3f45434c6b5e10:26
lkclthat sounds too long and likely that you've over-run 80 chars10:26
lkcli know.10:27
lkcl        # 3rd operand only needed when operation is a store10:28
lkcl        comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)10:28
lkclno, it can be left alone entirely10:28
lkclbecause if op_is_dcbz is set, then op_is_st will *not* be set10:29
lkcland therefore the 3rd operand will not be requested10:29
lkclrd.rel_o[2] will never be set10:29
lkclso i think it's ok10:32
lkclooo you juuust stayed within 80 char limit on op_is_st_or_dcbz :)10:33
tplatenSo no changes to undo, except whitespace?10:33
lkclit actually looks pretty all good.10:33
tplatenYes, my editor highlights anything above 80 chars.10:33
lkcli would have used "st_or_dcbz" as the variable name to keep it shorter, but it works fine10:34
lkclst_o is not being set to indicate output though10:35
lkcl        comb += self.st_o.eq(op_is_st)10:35
lkcli think it probably a good idea to set that equal to op_is_st_or_dcbz10:37
lkcland we just see how that goes10:37
lkcltplaten, you know how many times i redrew that LDST diagram at the gate level, by hand?  it was over 15 times :)10:43
tplatenYes, I know. I think I should do a redraw with DCBZ. It won't be correct when I try first.10:48
cesarI had an idea some time ago to replace the FSM in MultiCompUnit with a dataflow approach, see: (diagram on
cesar(maybe it could work to simplify LDSTCompUnit as well)11:49
tplatenI will have a look soon, but first I fix dcbz11:52
tplatenIn my case the PortInterface stays busy forever11:52
tplatenI agree with lkcl that this is a super idea, but I don't know how to implement that.12:26
tplatenIn the meanwhile I have fixed the last dcbz that I know about.12:27
cesarSure, it's low priority.12:35
cesarI hope to be able, sometime, to resume the task of improving the unit tests of MultiCompUnit and LDSTCompUnit, with formal verification even...12:38
cesarI find that reviewing/improving tests is a good way to learn/understand LibreSOC internals, before actually developing for it.12:41
tplatenI agree, but for today I am done.12:50
lkclcesar, in planning ahead for NGI POINTER, we have 6 months to get the MMU, L1 caches, Exceptions etc into shape15:35
lkclbut, we also need a faster core.15:35
lkcldo you think you could do a *really simple* (non-SVP64) in-order core?15:35
lkclpipelines, and with a "vector of outstanding expected writes to regs"?15:38
lkclon each issue, if any bit is set "1" for a reg, execution stalls15:39
lkclon each issue, any (new) write-regs set the bitvector for that reg to "1"15:39
lkclwhen the result pops out the end of a pipeline, the result is written to the regfile and its corresponding bitvector is cleared15:40
lkclLD/ST has to stall until the Address-Gen is completed and there is no possibility of "error" coming back from either Exception or actual Wishbone Bus error15:41
lkclthat's about it.15:41
lkclshould actually be able to re-use much of TestIssuer15:50
lkclwhich, originally, before adding SVP64, was under 400 lines15:50
lkclcesar, awesome.  it should actually be really straightforward, maybe (just maybe) even possible to split out FSM code from TestIssuer as shared classes18:17
lkclusing the ready-valid communication (forward-direction-only) as pipeline ready/valid.18:18
lkclthat possible thought was one of the reasons why i was trying to suggest keeping certain things with states as they are18:18
lkclrather than creating "back-links" between the FSMs18:19
lkclso that state information could always forward-progress18:19
lkclwhich of course is a critically essential prerequisite for running a pipeline18:19
lkclwith the complexity of SVP64 FSM18:19
lkcli think it may be easier / safer for now just to start again18:20
lkcloctavius, if you're interested in some wishbone work that needs doing (and can be paid) we have wishbone-streaming that needs inventing18:23
*** tplaten <tplaten!> has left #libre-soc19:39

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