| tplaten | I'm currently adding DCBZ support to src/soc/experiment/compldst_multi.py | 09:15 |
|---|---|---|
| tplaten | The line comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn) seems unclear to me | 09:16 |
| tplaten | also slg is 2 bits, the other signals are 3 bits | 09:16 |
| tplaten | slg = Cat(op_is_z, op_is_imm) | 09:16 |
| lkcl | tplaten, be very careful, it is one of the most extreme complex FSMs in the entire design | 10:21 |
| lkcl | it would be better if you didn't touch it at all, or, at least, added DCBZ by inputting zero as the immediate data from the outside | 10:22 |
| tplaten | I agree, so the input would be OP_ST for dcbz? | 10:22 |
| tplaten | if yes, I can undo my changes | 10:23 |
| lkcl | well, that's one thing that might be ok to do - let it have OP_ST/OP_DCBZ as the input option | 10:23 |
| lkcl | oh wait i already have op_is_dcbz | 10:23 |
| lkcl | or, you added it already | 10:24 |
| lkcl | op_is_st can be set if op == OP_ST *or* op == OP_DCBZ | 10:25 |
| tplaten | So I dont need op_is_st_or_dcbz | 10:25 |
| * lkcl thinks | 10:25 | |
| tplaten | here's the most critical commit: https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=b322acae923be19bc382cec4092d3f45434c6b5e | 10:26 |
| lkcl | that sounds too long and likely that you've over-run 80 chars | 10:26 |
| lkcl | i know. | 10:27 |
| lkcl | # 3rd operand only needed when operation is a store | 10:28 |
| lkcl | comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st) | 10:28 |
| lkcl | becomes | 10:28 |
| lkcl | no, it can be left alone entirely | 10:28 |
| lkcl | because if op_is_dcbz is set, then op_is_st will *not* be set | 10:29 |
| lkcl | and therefore the 3rd operand will not be requested | 10:29 |
| lkcl | rd.rel_o[2] will never be set | 10:29 |
| lkcl | so i think it's ok | 10:32 |
| lkcl | ooo you juuust stayed within 80 char limit on op_is_st_or_dcbz :) | 10:33 |
| tplaten | So no changes to undo, except whitespace? | 10:33 |
| lkcl | it actually looks pretty all good. | 10:33 |
| tplaten | Yes, my editor highlights anything above 80 chars. | 10:33 |
| lkcl | i would have used "st_or_dcbz" as the variable name to keep it shorter, but it works fine | 10:34 |
| lkcl | st_o is not being set to indicate output though | 10:35 |
| lkcl | comb += self.st_o.eq(op_is_st) | 10:35 |
| lkcl | i think it probably a good idea to set that equal to op_is_st_or_dcbz | 10:37 |
| lkcl | and we just see how that goes | 10:37 |
| lkcl | tplaten, you know how many times i redrew that LDST diagram at the gate level, by hand? it was over 15 times :) | 10:43 |
| tplaten | Yes, I know. I think I should do a redraw with DCBZ. It won't be correct when I try first. | 10:48 |
| cesar | I had an idea some time ago to replace the FSM in MultiCompUnit with a dataflow approach, see: https://bugs.libre-soc.org/show_bug.cgi?id=391 (diagram on https://bugs.libre-soc.org/attachment.cgi?id=65) | 11:45 |
| cesar | (maybe it could work to simplify LDSTCompUnit as well) | 11:49 |
| tplaten | I will have a look soon, but first I fix dcbz | 11:52 |
| tplaten | In my case the PortInterface stays busy forever | 11:52 |
| tplaten | I agree with lkcl that this is a super idea, but I don't know how to implement that. | 12:26 |
| tplaten | In the meanwhile I have fixed the last dcbz that I know about. | 12:27 |
| cesar | Sure, it's low priority. | 12:35 |
| cesar | I hope to be able, sometime, to resume the task of improving the unit tests of MultiCompUnit and LDSTCompUnit, with formal verification even... | 12:38 |
| cesar | I find that reviewing/improving tests is a good way to learn/understand LibreSOC internals, before actually developing for it. | 12:41 |
| tplaten | I agree, but for today I am done. | 12:50 |
| lkcl | cesar, in planning ahead for NGI POINTER, we have 6 months to get the MMU, L1 caches, Exceptions etc into shape | 15:35 |
| lkcl | but, we also need a faster core. | 15:35 |
| lkcl | do you think you could do a *really simple* (non-SVP64) in-order core? | 15:35 |
| lkcl | pipelines, and with a "vector of outstanding expected writes to regs"? | 15:38 |
| lkcl | on each issue, if any bit is set "1" for a reg, execution stalls | 15:39 |
| lkcl | on each issue, any (new) write-regs set the bitvector for that reg to "1" | 15:39 |
| lkcl | when the result pops out the end of a pipeline, the result is written to the regfile and its corresponding bitvector is cleared | 15:40 |
| lkcl | LD/ST has to stall until the Address-Gen is completed and there is no possibility of "error" coming back from either Exception or actual Wishbone Bus error | 15:41 |
| lkcl | that's about it. | 15:41 |
| lkcl | should actually be able to re-use much of TestIssuer | 15:50 |
| lkcl | which, originally, before adding SVP64, was under 400 lines | 15:50 |
| cesar | Sure! | 16:35 |
| lkcl | cesar, awesome. it should actually be really straightforward, maybe (just maybe) even possible to split out FSM code from TestIssuer as shared classes | 18:17 |
| lkcl | using the ready-valid communication (forward-direction-only) as pipeline ready/valid. | 18:18 |
| lkcl | that possible thought was one of the reasons why i was trying to suggest keeping certain things with states as they are | 18:18 |
| lkcl | rather than creating "back-links" between the FSMs | 18:19 |
| lkcl | so that state information could always forward-progress | 18:19 |
| lkcl | which of course is a critically essential prerequisite for running a pipeline | 18:19 |
| lkcl | but | 18:19 |
| lkcl | with the complexity of SVP64 FSM | 18:19 |
| lkcl | i think it may be easier / safer for now just to start again | 18:20 |
| lkcl | octavius, if you're interested in some wishbone work that needs doing (and can be paid) we have wishbone-streaming that needs inventing | 18:23 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=175 | 18:23 |
| *** tplaten <tplaten!~isengaara@55d4de47.access.ecotel.net> has left #libre-soc | 19:39 | |
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