Monday, 2021-11-01

* cesar has to read up on the Pipeline API, it's been a while...11:48
* cesar is half-seriously considering additional extensions to the nMigen language:12:49
cesar1) PipelineSignal: m.d.sync += S.eq(A+B). Every signal has valid/ready, automatically connected. S.valid is true when both A.valid and B.valid is true.12:51
cesar2. WishboneSignal: m.d.sync += buf.eq( A Wishbone bus read will be performed on address and the result deposited in buf.12:53
cesarm.d.sync += [B.eq(A), C.eq(B), D.eq(C)], where A,B,C,D are PipelineSignal, would build a buffered pipeline A->B->C->D.12:57
cesar.. or m.d.sync += [icache.addr.eq(pc), decode.opcode.eq(, regfile.ra.addr.eq(decode.instr.ra), regfile.rb.addr.eq(decode.instr.rb), execute.instr.eq(decode.instr), execute.ra.eq(, execute.rb.eq(, regfile.rt.addr.eq(decode.instr.rt),, pc.eq(execute.next_pc)]13:28
cesar(where every signal/port is PipelineSignal)13:29
*** Awoobis is now known as A_Dragon13:47
cesar(just an idea, nothing serious)14:57
lkclactually, you know the best place to do that?15:16
lkclvia the new AST abstraction i just added.15:16
lkclcesar, there are a ton of examples on the pipeline API :)  the actual functions needed are only 2: ispec and ospec, which create the data structure in and data structure out, respectively15:19
lkclthe only reason things are slightly more complicated for the ALUs is because, *on top* of that ridiculously simple API, i then added "regspecs" which *auto-generated* the ispec and ospec based on a separated data structure.15:20
lkclcesar, the completion of Type 1 (AST) and Type 2 (dsl.Module) abstraction that i did about 6 weeks ago means that you *don't have to modify or extend the nmigen language*16:32
lkclat all16:32
lkclas long as the proposed PipelineSignal obeys the "rules" (provides the prerequisite operators, which now includes PipelineSignal.__Cat__, PipelineSignal.__Assign__ etc.) nmigen is abstracted enough to accept that16:33
lkclthere is also no reason why "strong typing" should not be added in the same way.16:33
lkclincluding strong typing for Clock Signals (just as they are done in Bluespec)16:34
lkcland optimisation phases such as merging a series of static-allocated Slice, Part and Cat chains.16:35
*** kylel1 is now known as kylel16:35
cesarMaybe that (Type 1 and Type 2 abstractions) is what should be sent as an nMigen RFC, not SimdSignal itself. SimdSignal, along with PipelineSignal, WhishboneSignal, Clock Signal typing, etc., could be seen as use cases of that, making a strong argument, and not being just tied to a LibreSOC need.16:42
lkclcesar: it was.  however whitequark's "expert consultants" ordered whitequark to reject the entire RFC.18:07
lkclin the process causing whitequark to renege on an agreement made in April.18:08
lkclif whitequark had informed me of the outright rejection at the time rather than leaving it for six months, we could have planned properly18:08
lkclthe discussion that whitequark interrupted when i was explaining the RFC was about the abstraction, how to complete it, and the benefits of doing so18:09
lkcli did not get an opportunity to complete those discussions before censorship was enacted approximately 15 hours later.18:10
lkclhowever, during those discussions, whitequark made it clear that it is a DELIBERATE intention to terminate all and any possibility of the use of Liskov Substitution Principle - abstraction - within nmigen18:11
lkclall possibilities - PipelineSignal, WishboneSignal, PartitionedSignal, typing - are terminated with prejudice and by definition.18:12
lkclthis is an *active* choice - made by whitequark - to *define* nmigen language behaviour as being exclusively and solely scalar and in terms of what whitequark says is permitted18:12
tplatenI'm currently trying to run unit tests that use soc.simple.test.test_runner.TestRunner and get lots of UnusedElaboratables18:12
lkclall else is prohibited.18:12
lkcltplaten: what exactly are you running18:13
lkclwhat command?18:13
tplatenI wrote that unit test some month ago18:13
lkclthe more serious error is this18:14
lkclsoc/src/soc/fu/ldst/ DriverConflict: Signal '(sig dar)' is driven from multiple fragments: top.issuer.core.fus, top.issuer.core.l0; hierarchy will be flattened18:14
lkclwhich means exactly as it says: you've tried to drive dar from more than one location.18:15
lkclyou'll need to track that down (git bisect) to find out exactly what modifications you made which cause two separate code locations to try to drive it18:15
tplatenSince I never used git bisect before, I first read some tutorials18:21
* lkcl just doing manual checkouts18:21
lkcltplaten, put this at the end of
lkclPartitionedSignal = SimdSignal18:21
lkclcommit 9c58fe8b3ccce5123f5119d381ecc96f5152c11918:23
lkcl    add test_issuer_dcache.py18:23
lkcldarn it, have to check out an openpower-isa from that timeperiod as well18:24
lkclDate:   Sat Jul 24 13:25:49 2021 +020018:24
lkclbecause DCBZTestCase does not exist18:24
lkclah because you forgot to add it back then, to test_issuer_dcache.py18:24
lkclthat only happened 3 weeks later18:27
lkclcommit 63342580f71028d8272cd35cfa038da6e512293718:27
lkcl    add WIP DCBZTestCase18:27
tplatenDONE: tplaten, put this at the end of PartitionedSignal = SimdSignal18:31
lkcli'm currently exploring this commit commit 63342580f71028d8272cd35cfa038da6e512293718:31
lkcland, sigh, there's an error in the DIV FSM CompUnit, i have no idea why18:31
lkclgoing to set the units to not have a DIV ALU18:32
lkclfound a way to do that18:33
lkclok: as far back as 592a924f61e97 it looks like there's always been a DriverConflict18:36
lkcli'm going to see if i can get back to before the nmutil rename (ready_o -> o_ready)18:37
lkclcommit c17aa78fdd09eeefdb5d34ae5bde81c33fbef7a018:38
tplatenthat looks like an incomplete url18:38
lkcltplaten, it isn't18:38
lkclDate:   Tue Aug 24 11:14:24 2021 +010018:38
lkclthat's a nmutil commit, before the ready_o->o_ready rename18:38
lkclit's me doing "git diff > /tmp/f" followed by "scp /tmp/f"18:40
lkclstill a DriverConflict on commit cb49428fe18:40
lkcleven as far back as the original "add WIP DCBZTestCase"18:42
lkclcommit 63342580f710218:42
lkclAuthor: Tobias Platen <>18:42
lkclDate:   Mon Aug 16 20:02:06 2021 +020018:42
lkclthere have always been DriverConflicts.18:42
tplatenand I never noticed when running test code18:42
lkclas in: when you wrote the code, you wrote it with two simultaneous pieces of HDL trying to sync-drive the exact same Signal(s)18:43
lkclthat's probably because you didn't output the full error logs to a file18:43
lkclpython3 simple/test/ >& /tmp/f118:43
lkclyou have to output stderr as well as stdout18:43
lkclor use nohup18:43
lkclnohup python3 simple/test/test_issuer_dcache.py18:43
lkclthen check it carefully18:44
tplatenNo, I do not get that DriverConflict: Signal '(sig dar)' on my machine, I saw there is a commit message 'resolve DriverConflict in TstL0CacheBuffer, really bad hack' from May 1st18:55
tplatenBut that code looks that there is really a driver conflict18:55
tplatenBut that is not soc/src/soc/fu/ldst/loadstore.py18:58
lkclproblem "goes away"19:06
tplatenThe value is changed by MicrOp.OP_MTSPR and when an exception happens19:06
lkclmeaning, yes, there are two locations where dsisr, dar, priv_mode and real_mode are all set twice19:06
lkclyes.  and there should be an "input" value which reads from, rather than try to have it set n an "unauthorised" way.19:08
lkcli think this is down to splitting out the MMU as a separate FSM from microwatt loadstore.vhdl19:08
lkclit is not "exactly as microwatt"19:08
tplatencommented out the offending lines, now thinking how to implement this proper19:17
lkclwell, it's because we separated l_in.valid case l_in.op from and put it into instead19:20
lkclthis code19:24
lkclwas moved to fsm.py19:24
lkclwithout some "multiplexing", which, ironically, is just the exact same code, which happens to make sure to set l_in.valid,19:25
lkclyou can't do that19:25
lkclthose commands have to move to loadstore.py19:26
lkclthen does "passthrough" to it.19:26
tplatenI agree19:27
lkclbtw we're following that microwatt commit, f636bb7c19:28
lkclsoon after that, paul mackerras did a major update of loadstore, to a 3-stage pipeline.19:29
lkclwhich we definitely don't want to follow, the code gets horribly complex19:29
tplatenYes, I remember. I have to look at an older version of microwatt19:31
tplatenmaybe I do a commit in the libre-soc source code pointing to that microwatt version19:31
lkclif you can go ahead and copy the m.Switch(op.insn_type) over to loadstore.py19:31
lkcl            case l_in.op is19:32
lkclwhere's that data structure..19:33
*** tplaten <tplaten!> has left #libre-soc19:44

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