Friday, 2021-11-26

Veera[m]cached property  in functools was added with Python-3.8! And I have the default Python-3.7 installed with Buster03:41
lkclpython3 budget_sync10:17
lkclchecked that, you're right10:20
lkclprogrammerjake, ^ can you please remove cached_property from budget_sync10:21
*** henriok_ is now known as henriok11:56
ghostmansdHi folks, I have some issues upon running `sudo bash ../dev-env-setup/hdl-dev-repos-virtualenv`12:30
ghostmansdIs anyone familiar with this? It's been a while since I established the repos12:31
ghostmansdThat's for local setup, not talos12:32
ghostmansdSame for `sudo bash ../dev-env-setup/hdl-dev-repos`12:39
lkclgit submodule update.12:48
lkclit means you've not done "git pull" or "git submodule update" since tuesday.12:49
lkclghostmansd, ^12:49
ghostmansd[m]Not sure if I should; this soc repository is handled as part of hdl-dev-repos, isn't it?13:02
ghostmansd[m]lkcl: I suspect it happens on `make gitupdate`, it must've taken the wrong revision13:19
ghostmansd[m]No, even `git submodule update --init --recursive` doesn't help13:20
lkclsadoon_albader[m ran git pull and then submodule update and it worked fine14:58
lkclthere's been some changes to pinmux in the past 2 weeks14:59
lkcltoshywoshy, mattermost bridging seems to have stopped at about tuesday15:10
lkclVeera[m], you can look through the source code for the function "exts"15:25
lkclwith "grep -r"15:25
lkclor ctags -R in the top-level directory15:26
lkclthen ":tag exts" in vim15:27
lkclVeera[m], openpower.decoder.helpers. you could have also done, "find . -name ""15:35
Veera[m]lkcl: I found it beforehand16:40
Veera[m]lkcl: I git pulled both openpower-isa and soc repo16:41
Veera[m]ran make pywriter but now the tests are not finishing16:42
Veera[m]they are stalling at decode2execute init tmp <class 'openpower.decoder.decode2execute1.Decode2ToOperand'> None16:43
Veera[m]running make mkpinmux in soc repo gives error!!!17:24
Veera[m]Traceback (most recent call last):17:24
Veera[m]  File "src/", line 101, in <module>17:24
Veera[m]    pm, chip = jsoncreate.pinparse(ps, pinspec)17:24
Veera[m]  File "/home/vklr/src/soc/pinmux/src/", line 217, in pinparse17:24
Veera[m]    padbank[banknum] = name17:25
Veera[m]IndexError: list assignment index out of range17:25
Veera[m]make: *** [Makefile:10: mkpinmux] Error 117:25
Veera[m]And pinmux git log outputs commit 20ca612b2600530ce901009b3d1b9ef0e05b743817:25
Veera[m]The same problem ghostmansd has/had!17:26
Veera[m]ghostmansd[m]:  I solved the problem temporarily with: cd soc; cd pinmux; git checkout 1d16fd5b277d276f2e7603e888be359083cec09a; cd ..; make mkpinmux17:36
Veera[m]I think pinmux is work in progress for now and broken. You can ask lkcl andrey for more recent commit which works17:37
programmerjakelkcl: fixed budget-sync, you'll need to rerun setup.py18:09
Veera[m]programmerjake:  yes cached_property error has gone.18:54
Veera[m]programmerjake:  But there are other errors: KeyError: 'NLnet.2021-08-049.coriolis2'18:56
Veera[m]programmerjake:  And also budget allotment errors18:57
programmerjakeyeah, those errors mean that the new milestones need to be added to budget-sync-config.toml, as well as the inconsistent information corrected on bugzilla...note that #48 and #191 should be left unfixed19:15
programmerjakei'll fix that...19:15
programmerjakeVeera: ok, i fixed it. ignore the errors for #48, #191, and #589, we're aware of them and are intentionally leaving it that way. if other errors show up, check with @lkcl or fix the allocation in bugzilla if you messed it up by miscalculating19:42
lkcl2021-08-049 is a new grant19:51
lkclso is... #589.19:51
lkcl"NLnet.2021.02A.CryptoRouter" = { canonical_bug_id = 589 }19:53
lkcl"NGI POINTER Gigabit ASIC" = { canonical_bug_id = 690 }19:53
lkcl"NLnet.2021-08-049.coriolis2" = { canonical_bug_id = 748 }19:53
lkclbrilliant, thx programmerjake, saves me a job19:53
lkclERROR:root:Budget assigned to task including subtasks (cf_total_budget field) doesn't match calculated value: bug #589, calculated value 900019:54
lkclthat's because the cryptorouter one hasn't had the MoU signed yet19:54
ghostmansdlkcl: I'll need some help and clarification regarding and binutils. I'm checking sv_decode.vhdl and I think I can hack/copy sv_analysis to produce some C-compatible stuff, but I have no idea how it correlates with binutils, except for perhaps an opcode (and even there I'm not sure how to treat records like `-----10110`).20:00
ghostmansdI also don't get anything close to 10000 of instructions; $(wc -l openpower/isatables/sv_decode.vhdl) shows 348 lines, many of these are boilerplate.20:01
ghostmansdMy main question is, I don't understand what to use and how. I can generate some C table of structures, for sure, but I need to know which kind of info should be there.20:04
ghostmansdLet's consider some instructions, e.g. `extsw` and `extsw.`, which have entries in powerpc_opcodes. `extsw` I can also see in `sv_decode.vhdl` (there's none for `extsw.`, though).20:06
ghostmansdIt'd be great if we could dissect what should be the relevant definition for the structures, e.g. what `struct svp64_opcode_augmentation` entry should `extsw` and `extsw.` have.20:08
ghostmansdI assume we also need some check for `sv.` prefix so that it's considered, right?20:09
lkclghostmansd[m], ok let's go through it20:20
lkclis 10,748 lines long.20:21
lkclstarting from 4280, running to 10,748, so there are "only" 6,500 Power ISA instructions, not 10,000.20:22
lkclclearly it would be f****g stupid to even attempt to add SVP64 encoding to that, by hand.20:22
lkclparticularly when much of it is duplicated.20:23
ghostmansd[m]Yehyeh, binutils part I plus or minus get20:23
programmerjakelkcl, you allocated more money for #730 but forgot to update its parent20:23
ghostmansd[m]I have no fricking idea of what this VHDL is and how sv.whatever corresponds to a simple whatever20:24
programmerjakei'll do that20:24
lkcladd, add. addo, addo. they are all identical SVP64 encoding, so it would need 4 duplicate copies of hand-edited SVP64 information to be added to all 420:24
lkclthe VHDL itself is not important, it's the fact that it's an auto-generated table that's important20:25
lkclprogrammerjake, thx, just concentrating on binutils with ghostmansd[m]20:25
lkclso the basic principle is - as you can see in - which literally needs translating into c - is:20:26
lkcl"sv.add RT, RA, RB" instruction is encountered20:26
lkclthe fields RT, RA, and RB are now 7-bit, not 5-bit20:26
lkcl2 of those bits go into the 24-bit prefix.20:26
lkclthe remainder of the 5-bit fields *remains in the 32-bit opcode*, exactly as if it was a Power ISA 3.0 32-bit operation20:27
lkclthus, when the hardware (and simulator) encounters a 64-bit SVP64 Prefix, it:20:27
ghostmansd[m]Two more bits indicate the XLEN?20:27
lkcl1) extracts the 24-bit SV "RM" field from the first 32-bits20:28
lkcl2) **RECONSTRUCTS** the 7-bit register numbers based on 2-bits in SV "RM" and the 5-bit fields in the 32-bit Power ISA 3.0 instruction20:28
lkclyes, funnily enough20:28
lkclELWIDTH encoding -
lkclnow, where it gets bloody complicated is that, actually, those register number "enhancements" can either mark those (extended-to-7-bit) register numbers as either20:30
lkcl1) scalar20:30
lkcl2) vector20:30
lkclso that's actually *3* bits per register, not 2.20:30
lkclas you probably already worked out:20:30
lkclsay for e.g. FMAC, 3 bits times 4 registers (Rt RA RB RC) is 12 bits20:31
lkcland that's far too much20:31
lkclto cope with that....20:31
lkclwe have *two* different encodings for registers20:31
lkcland EXTRA320:31
lkclEXTRA2 is *only two* bits per register20:32
lkclEXTRA3 is *three* bits per register20:32
lkcland the program basically encodes20:32
lkclwhich instructions are encoded as EXTRA220:32
lkcland which are encoded as EXTRA320:32
lkclit also specifies the relationship / mapping between EXTRA2[0..3] and EXTRA3[0..2] to RA/RB/RC/RT/EA20:33
lkcland *that* is the information that is auto-generated by sv_analysis.py20:33
lkclwithout which it is literally impossible to decode the SV64 24-bit prefix20:33
lkcland if you tried to do it by hand you would create a total maintenance nightmare and also 100% guaranteed get it wrong simply through typing.20:34
lkclto get through that barrier, in python (sv/trans/, creates some CSV files which provide the "augmentation" information20:38
lkclwhich if you're not looking for it, isn't obvious, it's this one line of code that picks up all the CSV files:20:39
lkclactually, sorry, that's picking up the markdown pseudocode but is using the register encoding information from it20:41
lkclfield1: RT20:41
lkclfield2: RA20:41
lkclfield3: RB20:41
lkclfrom e.g. addi RT,RA,RB20:41
lkclyou'll be able to use sv/trans/ to double-check what you do.  the results should always be identical20:45
lkcllet's take an example from the auto-generated SVP64 CSV files20:45
lkcl 1 insn,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out220:45
lkcl  45 add,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,020:46
lkclPredicate-Type (number of predicates) is 1P - so only one predicate mask20:46
lkclE-Type (Extra Type) = EXTRA3.20:46
lkcltherefore, we have had it declared to us that from here Section 1220:47
lkclactually section 12.4 - 1P-2S1D (number of predicate masks: 1  number of source regs: 2   number of dest regs: 1)20:48
lkclthat ... err hang on, 12.4 isn't correct for that because the CSV file declares it as EXTRA3, the 12.4 table is for EXTRA2...20:49
lkclRdest_EXTRA310:12extends Rdest20:49
lkclRsrc1_EXTRA313:15extends Rsrc120:50
lkcltherefore, in the CSV file "0" column, you see d:RT20:50
lkcland in the "1" column you see "s:RA"20:50
lkcland in the "2" column you see "s:RB"20:51
lkclwhich, ha, that is Rsrc2_EXTRA3 which should be in bits 16:18 extending Rsrc220:51
lkcli need to edit the svp64 wiki 1 sec20:51
lkclnew section 12.4 RM-1P-2S1D20:53
lkclRdest_EXTRA310:12extends Rdest20:54
lkclRsrc1_EXTRA313:15extends Rsrc120:54
lkclRsrc2_EXTRA316:18extends Rsrc220:54
lkcl*now* it matches what's in the CSV file.20:54
lkclthe line 45 add,,1P,EXTRA3,.... says20:54
lkcl"to decode RT which is marked as destination (d:RT) you must use the EXTRA3 bits 10:12 which are in the 24-bit SVP64 prefix"20:55
lkcl"to decode RA which is marked as src1 (s:RA) you must use the EXTRA3 bits 13:15 which are in the 24-bit SVP64 prefix"20:55
lkcl"to decode RB which is marked as src2 (s:RB) you must use the EXTRA3 bits 16:18 which are in the 24-bit SVP64 prefix"20:56
lkclthere is *NOT* enough room in the actual 24-bit RM field for it to be self-describing20:56
lkclyou *HAVE* to partially-decode the v3.0 mnemonic.  sv.add ==> Power ISA v3.0 "add" instruction20:57
lkcl==> look up the SVP64 CSV file entry for "add"20:57
lkcl==> 45 add,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,020:57
lkcland THAT is why you need to augment the ppc_ops tables with pointers to SVP64 information struct svp64_augmentation_info20:58
lkclbecause you must20:58
lkcl1) identify the Power v3.0B operation FIRST20:58
lkcl2) look up the SVP64 information SECOND20:58
lkcl3) use the designation EXTRA2/3 and the d:RT s:RA (etc) information to decide what to put into bits 10:18.20:59
lkclit is very much a mundane by-rote task that is literally the translation of sv/trans/ into c.21:00
lkclit doesn't *actually* need "understanding" of SVP64 itself.21:00
lkclit's literally "if recognise these strings / ASCII characters, blat these binary 1s/0s into certain bit fields"21:01
lkcli would suggest starting small21:02
lkcldon't even bother at the moment with the reg number remapping.21:02
lkclstart with recognising say..21:03
* lkcl looking for some bitfields that are mandatory and unconditionally-positioned..21:03
lkclsection 7 "common RM fields"21:04
lkcl45 add,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,021:04
lkclSUBVL8:9Sub-vector length21:04
lkclif strcmp(sub_field, "vec2") { svp64_rm |= (1<<8 }21:05
lkclif strcmp(sub_field, "vec3") { svp64_rm |= (2<<8 }21:05
lkclif strcmp(sub_field, "vec4") { svp64_rm |= (3<<8 }21:05
lkclthat's it.21:05
lkclthat's SUBVL done.21:05
lkclequivalent python:21:06
cesarI remember gaining a much better undersranding of SVP64 when Luke presented it live, going over the wiki, topic by topic.21:23
cesar... but then, we were reviewing it, and had a wider audience...21:25
programmerjakelkcl: well, i'm trying to get my friend's printer to work for printing the stuff I need to sign for fundingbox, currently the black ink doesn't work at all, i may run out of time today so not get around to ternlogi, sorry23:24

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