| Chips4Makers[m] | lkcl: I don't have time ATM to look myself at code and do development. Need to work on std cell and IO for Sky130. | 10:29 |
|---|---|---|
| lkcl | Chips4Makers[m], not a problem, will take care of it. | 10:38 |
| lkcl | appreciate the insights | 10:46 |
| Chips4Makers[m] | My plan is still to integrate JTAG inside platform though. | 10:55 |
| lkcl | that will leave it as being completely impossible to run Simulate() | 10:59 |
| lkcl | we have just discovered this | 10:59 |
| lkcl | to "fix" this, the entirety of the BS regs must be set up - and connected - inside a top module - **BEFORE** calling Platform.build() | 11:00 |
| lkcl | i have tried extracting the fragment created by build() | 11:00 |
| lkcl | calling Simulate() on that post-build fragment **FAILS** due to Clock Domains having already been established by the build() process | 11:01 |
| lkcl | a second call to try to establish the clock domains **FAILS** | 11:01 |
| lkcl | you can also try to integrate JTAG inside the platform if you wish: whenever someone tries to run Simulate() on the resultant JTAG-enabled Boundary-scan-aware fragment, it will also fail | 11:03 |
| lkcl | i don't think anyone has ever tried to run nmigen Simulation() on the fragments created by Platform.build() before. | 11:04 |
| lkcl | Platform.build() is designed to be a one-way non-interactive replacement for Makefiles | 11:04 |
| lkcl | what i will do is: move the linking of the io back into the "normal" way so that it can be simulated | 11:05 |
| lkcl | and expose an API of pin-pads that can also be connected in the "normal" way | 11:06 |
| lkcl | this satisfies both requirements - to have JTAG appear to be "integrated inside the platform" - and also allow nmigen Simulation() | 11:07 |
| Chips4Makers[m] | As said I don't have time to investigate further ATM. | 11:16 |
| lkcl | then please: trust me to do it, and trust me when i say that problems have been encountered in the way that both of us originally would like to see this work | 11:21 |
| Chips4Makers[m] | When I have time (likely sometime next year) I will look at solving the simulation problem with integrated JTAG in platform rather than doing that outside Platform. | 11:28 |
| lkcl | hmmm, unfortunately, from a Project Management perspective, we have a team member waiting who cannot do anything (cannot write unit tests) because this isn't working. | 11:41 |
| lkcl | next year means at least 6-8 weeks which is time that at least one other person cannot do anything | 11:41 |
| lkcl | and that 6-8 weeks represents around 20% of the available time | 11:41 |
| lkcl | we cannot have a team member held up doing nothing for 6-8 weeks | 11:42 |
| lkcl | if you can look at it in such a way that converting from what we have to create does not create additional time / work to be converted (when we are under such insane time pressure) that would be great | 11:43 |
| Chips4Makers[m] | I don't say to wait for me; I just want to notify of what my plans are. | 11:46 |
| lkcl | appreciated. what i'm saying is: if we _did_ wait for you, it risks jeapordising the timescales.... therefore we can't. | 11:53 |
| * cesar is wondering, in soc/fu/branch/pipe_data.py, why the Branch Function Unit have a NIA port as an output, but no CIA on input (for PC relative branches). | 13:38 | |
| cesar | CIA seems instead to come from FU input record (soc/fu/branch/br_input_record.py) | 13:39 |
| cesar | What confuses me a bit is that there is a CoreState inside core.py, which includes the PC, and a Register File which also includes a PC. | 13:44 |
| cesar | What I'm hoping to do is cleanly partition the Pipelines (Fetch, Decode, Issue, Execute). In that sense, PC handling should be handled on Execute, exclusively, and propagated to the rest via the Pipeline API. | 13:48 |
| cesar | ... or PC, MSR, exceptions, etc. can maybe remain global, as they are now... | 14:06 |
| Veera[m] | lkcl: query about https://bugs.libre-soc.org/show_bug.cgi?id=50#c24 | 14:10 |
| Veera[m] | lkcl: actually there are 3 pics in there | 14:11 |
| Veera[m] | lkcl: Shall I have to convert 3 pics or 2 | 14:11 |
| Veera[m] | gpio_block.png, jtag-block.jpg and CH02-44.gif | 14:13 |
| Veera[m] | If I open a Bug task, what should I call it? | 14:13 |
| Veera[m] | And in which category to open? | 14:13 |
| lkcl | yes all three | 14:26 |
| lkcl | sub-bug of #50 | 14:26 |
| lkcl | mmm... "pinmux gpio diagrams" | 14:26 |
| cesar | When running python ~/src/soc/src/soc/simple/test/test_issuer.py nosvp64 --allow-overlap, I get | 14:30 |
| cesar | File "/home/cstrauss/src/soc/src/soc/simple/core.py", line 453, in connect_rdport | 14:30 |
| cesar | wvchk = wv.q_int # write-vec bit-level hazard check | 14:30 |
| Veera[m] | lkcl: Is there a way to find out in which bugs I have been put to CC list? | 14:30 |
| cesar | AttributeError: 'SRLatch' object has no attribute 'q_int' | 14:30 |
| Veera[m] | In my firefox and image-viewer jtag-block.jpg in bottom is corrupt I think. It's all red at bottom and hardly decipherable! | 14:33 |
| Veera[m] | <Veera[m]> "lkcl: Is there a way to find out..." <- Ok I found out. Advanced search in Bugzilla has a way! | 14:36 |
| lkcl | cesar, 1 sec | 14:38 |
| lkcl | cesar, git pull | 14:39 |
| lkcl | that's because i blanked it out so that you would know not to try to include that part | 14:39 |
| lkcl | Veera[m], ^ | 14:39 |
| Veera[m] | ok | 14:40 |
| lkcl | Veera[m], this one too | 15:27 |
| lkcl | https://libre-soc.org/docs/pinmux/i_o_io_tristate_jtag.JPG | 15:27 |
| Veera[m] | ok | 15:28 |
| cesar | "python ~/src/soc/src/soc/simple/test/test_issuer.py nosvp64 --allow-overlap general" is failing on "test_loop" | 16:24 |
| cesar | AssertionError: 12 != 15 : int reg 9 (sim) not equal (hdl) 'bc 4,10,-8'. got c expected f at pc 10 4 | 16:24 |
| cesar | Without --allow-ovelap, it passes. | 16:26 |
| lkcl | cesar: yes i haven't run it on general cases yet | 16:47 |
| lkcl | the only ones i've done are the hazards. | 16:47 |
| lkcl | the branch is the most likely cause of trouble | 16:47 |
| lkcl | Chips4Makers[m], sorted. | 16:56 |
| lkcl | https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/testing_stage1.py;h=ebb6c4c3918872e21dabca964bdc66016b90b220;hb=0009133fd29cbcc6fe6c189a7290bc4bfcee08ec | 16:56 |
| lkcl | when you've time ^ | 16:56 |
| lkcl | triple ResoureManagers. | 16:57 |
| lkcl | * two inside JTAG (one for core, one for pads) | 16:57 |
| lkcl | * one (inherited) in Platform | 16:57 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=50#c51 | 16:57 |
| lkcl | will tidy it up later, bulk of the work is done and concept is proven | 16:59 |
| lkcl | both requirements are satisfied. | 16:59 |
| _mepy | Hi | 19:24 |
| *** _mepy is now known as mepy | 19:28 | |
| lkcl | Chips4Makers[m], fantastic! https://www.linkedin.com/posts/staf-verhaegen-b3316b_retro-%C2%B5c-2021-test-tape-out-activity-6870721594424074241-U8SU | 19:55 |
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