Sunday, 2021-11-28

Chips4Makers[m]lkcl: I don't have time ATM to look myself at code and do development. Need to work on std cell and IO for Sky130.10:29
lkclChips4Makers[m], not a problem, will take care of it.10:38
lkclappreciate the insights10:46
Chips4Makers[m]My plan is still to integrate JTAG inside platform though.10:55
lkclthat will leave it as being completely impossible to run Simulate()10:59
lkclwe have just discovered this10:59
lkclto "fix" this, the entirety of the BS regs must be set up - and connected - inside a top module - **BEFORE** calling
lkcli have tried extracting the fragment created by build()11:00
lkclcalling Simulate() on that post-build fragment **FAILS** due to Clock Domains having already been established by the build() process11:01
lkcla second call to try to establish the clock domains **FAILS**11:01
lkclyou can also try to integrate JTAG inside the platform if you wish: whenever someone tries to run Simulate() on the resultant JTAG-enabled Boundary-scan-aware fragment, it will also fail11:03
lkcli don't think anyone has ever tried to run nmigen Simulation() on the fragments created by before.11:04 is designed to be a one-way non-interactive replacement for Makefiles11:04
lkclwhat i will do is: move the linking of the io back into the "normal" way so that it can be simulated11:05
lkcland expose an API of pin-pads that can also be connected in the "normal" way11:06
lkclthis satisfies both requirements - to have JTAG appear to be "integrated inside the platform" - and also allow nmigen Simulation()11:07
Chips4Makers[m]As said I don't have time to investigate further ATM.11:16
lkclthen please: trust me to do it, and trust me when i say that problems have been encountered in the way that both of us originally would like to see this work11:21
Chips4Makers[m]When I have time (likely sometime next year) I will look at solving the simulation problem with integrated JTAG in platform rather than doing that outside Platform.11:28
lkclhmmm, unfortunately, from a Project Management perspective, we have a team member waiting who cannot do anything (cannot write unit tests) because this isn't working.11:41
lkclnext year means at least 6-8 weeks which is time that at least one other person cannot do anything11:41
lkcland that 6-8 weeks represents around 20% of the available time11:41
lkclwe cannot have a team member held up doing nothing for 6-8 weeks11:42
lkclif you can look at it in such a way that converting from what we have to create does not create additional time / work to be converted (when we are under such insane time pressure) that would be great11:43
Chips4Makers[m]I don't say to wait for me; I just want to notify of what my plans are.11:46
lkclappreciated.  what i'm saying is: if we _did_ wait for you, it risks jeapordising the timescales.... therefore we can't.11:53
* cesar is wondering, in soc/fu/branch/, why the Branch Function Unit have a NIA port as an output, but no CIA on input (for PC relative branches).13:38
cesarCIA seems instead to come from FU input record (soc/fu/branch/
cesarWhat confuses me a bit is that there is a CoreState inside, which includes the PC, and a Register File which also includes a PC.13:44
cesarWhat I'm hoping to do is cleanly partition the Pipelines (Fetch, Decode, Issue, Execute). In that sense, PC handling should be handled on Execute, exclusively, and propagated to the rest via the Pipeline API.13:48
cesar... or PC, MSR, exceptions, etc. can maybe remain global, as they are now...14:06
Veera[m]lkcl: query about
Veera[m]lkcl: actually there are 3 pics in there14:11
Veera[m]lkcl: Shall I have to convert 3 pics or 214:11
Veera[m]gpio_block.png, jtag-block.jpg and CH02-44.gif14:13
Veera[m]If I open a Bug task, what should I call it?14:13
Veera[m]And in which category to open?14:13
lkclyes all three14:26
lkclsub-bug of #5014:26
lkclmmm... "pinmux gpio diagrams"14:26
cesarWhen running python ~/src/soc/src/soc/simple/test/ nosvp64 --allow-overlap, I get14:30
cesarFile "/home/cstrauss/src/soc/src/soc/simple/", line 453, in connect_rdport14:30
cesarwvchk = wv.q_int # write-vec bit-level hazard check14:30
Veera[m]lkcl: Is there a way to find out in which bugs I have been put to CC list?14:30
cesarAttributeError: 'SRLatch' object has no attribute 'q_int'14:30
Veera[m]In my firefox and image-viewer jtag-block.jpg in bottom is corrupt I think. It's all red at bottom and hardly decipherable!14:33
Veera[m]<Veera[m]> "lkcl: Is there a way to find out..." <- Ok I found out. Advanced search in Bugzilla has a way!14:36
lkclcesar, 1 sec14:38
lkclcesar, git pull14:39
lkclthat's because i blanked it out so that you would know not to try to include that part14:39
lkclVeera[m], ^14:39
lkclVeera[m], this one too15:27
cesar"python ~/src/soc/src/soc/simple/test/ nosvp64 --allow-overlap general" is failing on "test_loop"16:24
cesarAssertionError: 12 != 15 : int reg 9 (sim) not equal (hdl) 'bc 4,10,-8'.  got c  expected f at pc 10 416:24
cesarWithout --allow-ovelap, it passes.16:26
lkclcesar: yes i haven't run it on general cases yet16:47
lkclthe only ones i've done are the hazards.16:47
lkclthe branch is the most likely cause of trouble16:47
lkclChips4Makers[m], sorted.16:56
lkclwhen you've time ^16:56
lkcltriple ResoureManagers.16:57
lkcl* two inside JTAG (one for core, one for pads)16:57
lkcl* one (inherited) in Platform16:57
lkclwill tidy it up later, bulk of the work is done and concept is proven16:59
lkclboth requirements are satisfied.16:59
*** _mepy is now known as mepy19:28
lkclChips4Makers[m], fantastic!

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