Saturday, 2021-12-04

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tplatenI just fixed wait_addr15:24
lkcltplaten, excellent15:24
* lkcl checking15:26
lkcli broke something15:26
lkcltplaten, confirmed working.15:28
lkcli have DSISR / DAR set/get working15:28
lkclfollowed (roughly) the style of MMU, which is:15:28
tplatennow I have a look at test_issuer_mmu.py15:28
lkcl* a m_in.mtspr signal which says to the receiver "please change this SPR numbered m_in.sprn"15:29
lkcl* combinatorial read of the SPR15:29
lkclreading is fine15:29
lkclbut writing has to be protected by that "if request-to-set" flag15:29
lkclthis works15:30
lkclpython3 simple/test/test_issuer_mmu.py nosvp64 >& /tmp/f115:30
lkclthe only error in that being one of the memory addresses, pc=4 not 0x30015:30
lkclhave to work out why15:30
lkclcase_5_ldst_exception - that's not matching the PC15:31
lkclahh it's the *simulation* that's not raising the misalignment exception, how amusing15:42
lkclwait... it's not a misaligned, is it - it's a... virtmode one15:44
lkclahh there's no exceptions raised in the simulator radixmmu.py15:46
tplatenWhen I run test_issuer_mmu.py with nosvp64, I get DriverConflict: Signal '(sig cur_pc)' is driven from multiple fragments: top.issuer, top.issuer.fetch15:48
lkclyes, ignore it15:48
tplatenI'm now having a look at issuer_simulator.vcd15:49
* lkcl resting15:50
lkcly15:50
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/radixmmu.py;h=c647777f325c137e95ce534b331dff2262e22267;hb=958cb90a00a45a4ee756b3cab323eb64cb4baf72#l31816:02
lkclthis code is missing LDST RADIX exceptions16:02
lkclwhich needs to be more like this16:03
lkclhttps://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radixwalk.cc16:03
lkclthat'll be fun16:05
tplatenI'll have a look at that code.16:06
lkcltplaten, we're going to need some unit tests that actually have a virtual memory pagetable set up16:06
lkclusing the wb_get function to pre-initialise the memory16:06
lkcli don't want to jump to running this microwatt test quite just yet16:07
lkclhttps://github.com/antonblanchard/microwatt/blob/3edc95eea50ef5520b6e399b1b9409555204933d/tests/mmu/mmu.c16:07
lkclalthough that's the ultimate goal here16:07
tplatenI have been thinking weather it possible to run that code on https://git.libre-soc.org/?p=kvm-minippc.git16:10
tplatenwriting pagetables by hand is hard, I have a look at that one that came with the MMU test case from microwatt16:14
lkclyes, there was one we did which had the examples from gem5-experimental radixwalk.cc16:24
lkclit can be reused, easily, no need to write it again16:25
lkcland that gives an advantage that the exact same data is expected16:25
lkclactually probably even use the exact same test case from ISACaller tests16:25
tplatenI agree16:26
lkclradixmmu.py, there are plenty of locations returning strings - return "invalid"16:26
lkclthese need instead to be "raise MemException("invalid")"16:26
lkclfollowed by catching that in caller.py16:26
lkcland calling the appropriate self.TRAP(....) with e.g. 0x300 or 0x380 etc. etc. etc. just like in ...16:27
lkclactually, probably just setting ldst_exc.instr_fault etc. etc.16:28
lkcli should probably take care of that, ISACaller is a bit of a pig16:30
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