| tplaten | I just fixed wait_addr | 15:24 |
|---|---|---|
| lkcl | tplaten, excellent | 15:24 |
| * lkcl checking | 15:26 | |
| lkcl | i broke something | 15:26 |
| lkcl | tplaten, confirmed working. | 15:28 |
| lkcl | i have DSISR / DAR set/get working | 15:28 |
| lkcl | followed (roughly) the style of MMU, which is: | 15:28 |
| tplaten | now I have a look at test_issuer_mmu.py | 15:28 |
| lkcl | * a m_in.mtspr signal which says to the receiver "please change this SPR numbered m_in.sprn" | 15:29 |
| lkcl | * combinatorial read of the SPR | 15:29 |
| lkcl | reading is fine | 15:29 |
| lkcl | but writing has to be protected by that "if request-to-set" flag | 15:29 |
| lkcl | this works | 15:30 |
| lkcl | python3 simple/test/test_issuer_mmu.py nosvp64 >& /tmp/f1 | 15:30 |
| lkcl | the only error in that being one of the memory addresses, pc=4 not 0x300 | 15:30 |
| lkcl | have to work out why | 15:30 |
| lkcl | case_5_ldst_exception - that's not matching the PC | 15:31 |
| lkcl | ahh it's the *simulation* that's not raising the misalignment exception, how amusing | 15:42 |
| lkcl | wait... it's not a misaligned, is it - it's a... virtmode one | 15:44 |
| lkcl | ahh there's no exceptions raised in the simulator radixmmu.py | 15:46 |
| tplaten | When I run test_issuer_mmu.py with nosvp64, I get DriverConflict: Signal '(sig cur_pc)' is driven from multiple fragments: top.issuer, top.issuer.fetch | 15:48 |
| lkcl | yes, ignore it | 15:48 |
| tplaten | I'm now having a look at issuer_simulator.vcd | 15:49 |
| * lkcl resting | 15:50 | |
| lkcl | y | 15:50 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/radixmmu.py;h=c647777f325c137e95ce534b331dff2262e22267;hb=958cb90a00a45a4ee756b3cab323eb64cb4baf72#l318 | 16:02 |
| lkcl | this code is missing LDST RADIX exceptions | 16:02 |
| lkcl | which needs to be more like this | 16:03 |
| lkcl | https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radixwalk.cc | 16:03 |
| lkcl | that'll be fun | 16:05 |
| tplaten | I'll have a look at that code. | 16:06 |
| lkcl | tplaten, we're going to need some unit tests that actually have a virtual memory pagetable set up | 16:06 |
| lkcl | using the wb_get function to pre-initialise the memory | 16:06 |
| lkcl | i don't want to jump to running this microwatt test quite just yet | 16:07 |
| lkcl | https://github.com/antonblanchard/microwatt/blob/3edc95eea50ef5520b6e399b1b9409555204933d/tests/mmu/mmu.c | 16:07 |
| lkcl | although that's the ultimate goal here | 16:07 |
| tplaten | I have been thinking weather it possible to run that code on https://git.libre-soc.org/?p=kvm-minippc.git | 16:10 |
| tplaten | writing pagetables by hand is hard, I have a look at that one that came with the MMU test case from microwatt | 16:14 |
| lkcl | yes, there was one we did which had the examples from gem5-experimental radixwalk.cc | 16:24 |
| lkcl | it can be reused, easily, no need to write it again | 16:25 |
| lkcl | and that gives an advantage that the exact same data is expected | 16:25 |
| lkcl | actually probably even use the exact same test case from ISACaller tests | 16:25 |
| tplaten | I agree | 16:26 |
| lkcl | radixmmu.py, there are plenty of locations returning strings - return "invalid" | 16:26 |
| lkcl | these need instead to be "raise MemException("invalid")" | 16:26 |
| lkcl | followed by catching that in caller.py | 16:26 |
| lkcl | and calling the appropriate self.TRAP(....) with e.g. 0x300 or 0x380 etc. etc. etc. just like in ... | 16:27 |
| lkcl | actually, probably just setting ldst_exc.instr_fault etc. etc. | 16:28 |
| lkcl | i should probably take care of that, ISACaller is a bit of a pig | 16:30 |
| *** tplaten <tplaten!~isengaara@55d46087.access.ecotel.net> has left #libre-soc | 17:25 | |
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