| *** AAAAA_DRAGON is now known as A_Dragon | 09:01 | |
| * lkcl dealing with the spaghetti of dcache.py and icache.py | 16:39 | |
| lkcl | wooow | 16:39 |
|---|---|---|
| lkcl | :) | 16:39 |
| tplaten | having a look at icache and mmu.py, l_in.iside needs to be set to update icache | 18:05 |
| tplaten | that is part of LoadStore1ToMMUType | 18:06 |
| lkcl | octavius, just saw the puzzle about uart. | 19:25 |
| lkcl | i have no idea, i'll take a look | 19:25 |
| octavius | sure | 19:25 |
| lkcl | sorted | 19:29 |
| lkcl | i printed out jtag.boundary_pads.keys() | 19:29 |
| lkcl | and saw something named | 19:29 |
| lkcl | uart_0__tx | 19:30 |
| lkcl | and uart_0__rx | 19:30 |
| octavius | ok | 19:32 |
| lkcl | next is flipping the boundary scan bits | 19:33 |
| octavius | Ok, I'll give that test a look-over again | 19:34 |
| lkcl | remember that the JTAG-tester is *de-coupled* - entirely - from the unit being tested | 19:35 |
| lkcl | as in: in a "real" system you would LITERALLY have four wires between the JTAG test program and the ASIC being tested | 19:36 |
| lkcl | therefore it is necessary to "reproduce" the information about which pins are which | 19:36 |
| lkcl | and to create the "sequence" of IO pads - the order - entirely *from scratch* | 19:36 |
| lkcl | i.e. from a "specification" | 19:36 |
| lkcl | guess what that specification is? | 19:36 |
| lkcl | the resource! | 19:37 |
| octavius | That sounds like hell XD | 19:37 |
| lkcl | create_resource() creates the list of information sufficient to re-create the entire list of the IO shift register indices | 19:37 |
| lkcl | actually i already did it, successfully. | 19:37 |
| lkcl | it's just not obvious / documented | 19:38 |
| lkcl | because i haven't had time | 19:38 |
| octavius | so how can I run it? | 19:38 |
| octavius | Do you have a script you ran? | 19:38 |
| octavius | at least a terminal history? | 19:38 |
| lkcl | over a year ago | 19:39 |
| octavius | So what should I do then lkcl? | 19:42 |
| lkcl | jtag boundary scan. flip the bits that re-route pads/core to the shift register | 19:43 |
| lkcl | yield srv_dut.ios[0].pad.i.eq(1) | 19:45 |
| lkcl | note: i have changed that to the *NAME* of the io pad. see jtag.py | 19:45 |
| lkcl | JTAG.add_pins | 19:45 |
| lkcl | self.ios[pin_name] = io | 19:45 |
| lkcl | that used to be a NUMBER | 19:45 |
| lkcl | it is now a **NAME** | 19:45 |
| octavius | So, still inside testing_stage1.py (just controlling the JTAG chain using Simulation())? | 19:46 |
| lkcl | completely separate unit test, yes. | 19:49 |
| octavius | ok sure | 19:49 |
| lkcl | use print top.jtag.ios.keys() | 19:49 |
| octavius | thanks | 19:49 |
| lkcl | don't try a separate process like in test_jtag_tap_srv.py | 19:50 |
| lkcl | use blinker top.jtag | 19:50 |
| octavius | Oh yeah, I'm not even going there XD | 19:50 |
| lkcl | but | 19:50 |
| octavius | that's a whole can of worms | 19:50 |
| lkcl | do use the jtag_set_reset() and other functions | 19:51 |
| lkcl | because you will waste a lof of time recreating those | 19:51 |
| octavius | But I still need a clock for the shift register, right? | 19:51 |
| lkcl | yes. just use sync domain | 19:51 |
| octavius | So just take the system clock for that? | 19:51 |
| octavius | sure | 19:51 |
| lkcl | yes. | 19:51 |
| lkcl | jtag_set_reset() etc. automatically flip the jtag.tck line for you | 19:52 |
| octavius | ok | 19:53 |
| lkcl | which is why i said, don't try to recreate those functions, you will quickly get into hell | 19:53 |
| octavius | I figured as much :) | 19:53 |
| octavius | Or perhaps more like :') | 19:53 |
| *** tplaten <tplaten!~isengaara@55d48f6c.access.ecotel.net> has left #libre-soc | 20:00 | |
| lkcl | wha-howww, big update to dcache.py to use Memory (SRAMs) | 23:24 |
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