Tuesday, 2021-12-21

lkclaw, doh, when compiling to verilog with an MMU it helps to actually pass the correct option inside issuer_verilog.py to actually create an MMU15:58
lkclhoo that was scary: loadavg jumped to 420 when compiling with verilator16:37
octaviusHi, long time no chat. I'll start catching up on the bug emails today. Is there a meeting this evening?19:03
programmerjakeyes, there is a meeting today19:10
lkclmeeting 10min21:48
lkcltoshywoshy, programmerjake octavius cesar mikolajw jn lxo sadoon_albader[m21:49
lkclanyone else if they'd like to21:49
octaviusDavid and I are in21:49
octaviusMy gitlab if you need it luke: https://gitlab.com/technepisteme22:49
lkcloctavius, star23:50

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