Thursday, 2022-01-20

programmerjakea "process" in yosys is basically a verilog `always` statement that yosys hasn't yet translated to gates. nmigen probably shouldn't have been designed to generate them, and generate gates directly instead because they are basically intended just for use by the verilog front-end and copy verilog's quirks, limitations, and bugs...nmigen generates processes instead of gates because they look nicer when reading verilog that yosys outputs.03:50
programmerjakeI found that in the nmigen/yosys docs somewhere, I forgot where.03:51
programmerjakein particular, if the verilog front-end can't generate a particular form of process, then that form of process is not super likely to work correctly and isn't/wasn't a priority for fixing in yosys.03:53
programmerjakeif you want to see what a process looks like, you can read the rtlil for it, it's basically a nested set of switches03:54
octaviusThanks for the explanation Jacob! Makes a lot more sense now. And I'll make sure to modularise when it stops making sense Luke.12:28
*** henriok_ is now known as henriok13:47
lkcli think i have de-messed-up the SPRs, now, after a rather intrusive reorg of SPRs18:49
lkclDEC and TB have moved to StateRegs, which makes sense from a pipelining perspective because they're used by PowerDecoder2 to determine if timer/watchdog interrupts go off18:50
lkclthat leaves enough space to expand FastRegs to 16 and move all of the microwatt-implemented SPRs into it18:50
lkclwhich in turn makes it easy to be fully compatible with microwatt DMI register-dumping18:51
lkcli messed up TB though. sigh. reading from the wrong regfile, the linux kernel does an early calibration of the timer and it was getting zero - infinite loop.18:52

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