kanzure | https://github.com/internet2-WG/rust-aluvm | 00:33 |
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lkcl | i love their code. "we don't have a Code. we're responsible people. get over it" :) | 10:43 |
programmerjake | imho they are a little too negative on wasm in their comparison -- for instance, they claim wasm is only supported on the internet --- that's just not true, wasm is specifically designed to run outside of web browsers too -- e.g. wamr runs on a Cortex-M7 microcontroller | 10:49 |
programmerjake | https://github.com/bytecodealliance/wasm-micro-runtime#supported-architectures-and-platforms | 10:50 |
openpowerbot | [slack] <github> signin | 10:50 |
programmerjake | also they claim wasm has undefined behavior, which, assuming they mean C-style UB is also false. a compiler targetting wasm might have UB but that's compiler-level UB, not wasm-level | 10:53 |
programmerjake | wasm itself is specified such that the wasm vm will trap instead of causing UB (a trap is basically equivalent to a sigsegv except it's more controlled and the program embedding the wasm vm can recover from that) | 10:56 |
lkcl | kanzure, the spec's incomplete, if this is all there is https://github.com/Internet2-WG/aluvm-spec | 11:12 |
lkcl | having to examine source code in order to find the list of opcodes is not filling me with confidence https://github.com/Internet2-WG/rust-aluvm/blob/master/src/isa/opcodes.rs | 11:15 |
lkcl | making its evaluation challenging | 11:15 |
lkcl | however we have big-integer math, so 4096-bit add/mul/div is not a problem | 11:16 |
lkcl | the mul/div is scalar-vector so a for-loop on top of that gives mul/div vector-vector (Knuth Algorithms D and M) | 11:16 |
lkcl | with 128 64-bit registers, up to 512-bit big-int add can be done comfortably in regs (because it takes QTY 16of 64-bit regs to do a 512-bit add), anything more than that can be done either | 11:18 |
lkcl | "uncomfortably", or by LD/ST (lots of register spill) | 11:18 |
programmerjake | 32x64-bit bigint add should be easily achievable in-registers... | 11:20 |
programmerjake | because the dest can be one of the src vectors | 11:21 |
ghostmansd[m] | > not filling me with confidence | 12:43 |
ghostmansd[m] | ...as well as the fact that it's written in Rust :-D | 12:43 |
ghostmansd[m] | Just willing to attract programmerjake attention lol | 12:43 |
ghostmansd[m] | Ok, just kidding, programmerjake, a friendly nitpicking :-) | 12:44 |
lkcl | writing meaningful non-ambiguous and complete specifications is... frickin hard | 13:13 |
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