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| programmerjake | lkcl: fixed and pushed to sv_maxu_works branch, waiting for ci to pass then I'll push to master: https://salsa.debian.org/Kazan-team/mirrors/openpower-isa/-/jobs/3172607 | 08:27 |
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| ghostmansd | lkcl, I've raised some disassembly-related tasks, currently not bound to anything, but groupped together. Some of them are already implemented (except for perhaps some future tuning); others are on track. | 09:39 |
| ghostmansd | https://bugs.libre-soc.org/show_bug.cgi?id=917 | 09:39 |
| ghostmansd | https://bugs.libre-soc.org/show_bug.cgi?id=921 | 09:53 |
| ghostmansd | another task of minor priority, but still likely essential if we want to compare assembly listings between objdump and pysvp64dis | 09:54 |
| programmerjake | doesn't objdump have a -M raw flag or something, that makes it not use aliases? | 09:55 |
| ghostmansd | it might be, I'm not sure | 10:02 |
| ghostmansd | anyway we'll likely have to support aliases anyway, including asm itself | 10:02 |
| programmerjake | yeah, i was very sad to not be able to use aliases when writing the utf-8 validator...it made it take probably 15% longer since i had to figure out what the unaliased instruction operands were, particularly annoying for branch conditions | 10:09 |
| programmerjake | other stuff i just now noticed (again?) when reading through int_fp_mv: the description of how fmvtgs/fmvfgs are incorrect, they do *not* act like frsp in any way. they use the lfs and stfs semantics which use the SINGLE and DOUBLE operations -- they do not round, set flags, or anything like that | 10:18 |
| programmerjake | lkcl: can i fix the descriptions for those? | 10:18 |
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| programmerjake | basically fmvfgs is equivalent to stw followed by lfs, and fmvtgs is equivalent to stfs followed by lwz | 10:21 |
| lkcl | there is no list of aliases. it is too much. this is not binutils. | 10:24 |
| lkcl | programmerjake, sure yes go for it on the fmvfgs. those all need to be drastically reduced to maximum 4 instructions, with say a 5-bit "mode" | 10:25 |
| lkcl | otherwise the IBM Architect Opcode Allocation Team are going to freak out | 10:25 |
| lkcl | ghostmansd[m], we don't have the time or resource to do aliases. i've closed the bugreport you raised. if there was a machine-readable list already in the spec i would hesitate but say "yes go for it" | 10:26 |
| lkcl | with that task requiring LITERALLY days possibly WEEKS to go over the entire 1,300 page spec the answer has to be a hard stone-cold "no" | 10:26 |
| lkcl | programmerjake, you'll just have to live with the lack of aliases, like i and everyone else has, for 2 years. | 10:27 |
| programmerjake | sadness, branch conditions are a pain... | 10:27 |
| lkcl | ghostmansd[m], brilliant on the bugreports. cross-linking them to as many other related things makes sure they are not "lost in the noise" | 10:27 |
| lkcl | programmerjake, yep. tough. computing the branch offset is a total pain, too. | 10:28 |
| lkcl | that's binutils's job | 10:28 |
| lkcl | markos was able to use an early version of ghostmansd's binutils-svp64 branch on the mp3 assembler | 10:28 |
| programmerjake | oh, i solved that, see the utf8 validation script, it adds a bunch of .set at the end for all the labels | 10:29 |
| lkcl | ahh very cool. | 10:29 |
| lkcl | i will raise a bugreport on the OPF ISA WG tracker that a machine-readable list of aliases is missing | 10:29 |
| programmerjake | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/algorithms/svp64_utf_8_validation.py;h=afcbde6809917ba138a15dad733ade4411b75a3e;hb=HEAD#l279 | 10:30 |
| * lkcl re-running tests now for that one, jacob | 10:30 | |
| lkcl | nice. | 10:30 |
| programmerjake | ah, it should work, ci passed | 10:31 |
| lkcl | i am always double-checking | 10:31 |
| programmerjake | k | 10:31 |
| lkcl | with /usr/bin/python3.7 having actually segfaulted (core-dumped, not a bullshit-oh-err-a-runtime-python-exception-is-a-crash-omg-omg) | 10:32 |
| programmerjake | if you are running pytest, you need SILENCELOG otherwise it runs out of memory due to the huge stdout logs, >14GB for me last i checked | 10:32 |
| lkcl | i am now paranoid about duplicating tests | 10:32 |
| lkcl | works perfectly well without it. | 10:32 |
| lkcl | lkcl@fizzy:~/src/libresoc/openpower-isa/src/openpower/decoder/isa$ !noh | 10:32 |
| lkcl | nohup pytest-3 -v -n auto | 10:32 |
| lkcl | nohup: ignoring input and appending output to 'nohup.out' | 10:32 |
| programmerjake | well, have fun using all your ram then! | 10:33 |
| lkcl | cranks the loadavg on my laptop up to 20 and makes browsers completely unresponsive, but it doesn't run out of memory | 10:33 |
| programmerjake | it's a known bug in pytest | 10:33 |
| lkcl | htop: | 10:33 |
| lkcl | Mem 32311/64027MB | 10:33 |
| lkcl | :) | 10:33 |
| lkcl | not a problem :) | 10:34 |
| programmerjake | well, for everyone with <64GB ram, it is a problem. also the tests probably run a lot faster when SILENCELOG=1 | 10:34 |
| lkcl | 2TB NVMe SSD... | 10:35 |
| programmerjake | uuh, that's not ram... | 10:36 |
| lkcl | we really do need budget allocations for seriously-beefy-HW for everyone | 10:36 |
| programmerjake | pytest stores stdout logs in ram, not on disk | 10:36 |
| lkcl | ahh | 10:36 |
| programmerjake | and the bug is it doesn't discard the logs for passed tests until the very end | 10:37 |
| programmerjake | well, if we're getting beefy hardware, the ryzen 7950x is coming out soon, 5.7ghz | 10:38 |
| programmerjake | launches on 9/27/2022 | 10:41 |
| programmerjake | sept 9 | 10:41 |
| programmerjake | sept 27, sorry misread | 10:41 |
| lkcl | oh btw you saw i updated comment 0 https://bugs.libre-soc.org/show_bug.cgi?id=899 | 10:42 |
| lkcl | frickin large list, feel free to prioritise / cut it back (drastically) if necessary | 10:42 |
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| lkcl | e.g. leave out the hypot bunch for example, just like in the original proposal, some of them are optional/obscure | 10:43 |
| * lkcl still feeling completely overwhelmed, haven't got to parallel-reduction or pack-unpack *at all* | 10:44 | |
| lkcl | ISA WG meeting went well today. can't say what was in it, but at least the External RFC Process is now public | 10:45 |
| lkcl | ============ 240 passed, 4 skipped, 620 warnings in 852.79 seconds ============ | 10:54 |
| lkcl | test_issuer.py still underway | 10:54 |
| programmerjake | fixed the fpr<->gpr move instructions' semantics: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=b7174adc52b41f12d98f350af00220a39f895860 | 11:01 |
| programmerjake | merging them all into fewer instructions can be done later | 11:02 |
| programmerjake | though i'll note we really only have 6 instructions: fishmv, fmvis, fmvtg[s][.], fmvfg[s][.], fcvtfg[u][wd][s][.], and fcvt[s]tg[u][wd][.], they all just have a bunch of options -- just like add, add., addo, and addo. | 11:08 |
| programmerjake | where [wd] means pick either w or d, and [s] means s is optional for any character s | 11:09 |
| programmerjake | imho none of those 6 instructions should be merged one of the other 6 instructions, they are all very different operations. | 11:12 |
| programmerjake | that'd be kinda like trying to merge fmv and add, it just doesn't make sense | 11:13 |
| programmerjake | we could restructure the page to emphasize how it's really only 6 instructions though, imho we should keep all the different mnemonics though | 11:14 |
| programmerjake | lkcl, read through comment #0 of bug 899, ya missed the atan2[pi] and powers table | 11:18 |
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| programmerjake | i added the atan2[pi] table to comment #0 | 11:27 |
| lkcl | yes 6 is great, 24 is not. they're already freaking out | 11:55 |
| lkcl | aliases for the stack of things currently listed. but as a separate much smaller table, again, to avoid freak-out-overwhelm | 11:56 |
| lkcl | good catch on 2-op table. | 11:57 |
| programmerjake | well, it's 4am, gn | 11:57 |
| lkcl | i updated as well. | 11:57 |
| lkcl | ok. | 11:57 |
| lkcl | nicely done | 11:57 |
| lkcl | night | 11:57 |
| ghostmansd[m] | lkcl, thanks for sorting out the bugs | 12:19 |
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| ghostmansd | It took me a while to realize why code stopped working with target_addr, and only then I recalled that target_addr no longer exists. :-) | 12:57 |
| ghostmansd | Already switched to real fields, LI and BD. | 12:57 |
| lkcl | ghostmansd, :) | 13:14 |
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| ghostmansd | lkcl, you forgot to change svbranch respectively | 15:36 |
| ghostmansd | I know this is WiP, but anyway | 15:36 |
| ghostmansd | I pushed two commits, both shouldn't break anything, but please let me know if you have issues. First commit skips empty operand entries in pagereader, the second replaces svbranch.mdwn target_addr with BD. | 15:41 |
| ghostmansd | Both changes hold me, and seem like needed in master. | 15:42 |
| lkcl | svbranch? que? what svbranch? | 16:03 |
| lkcl | ghostmansd, oh - yes. svbranch.mdwn | 16:03 |
| lkcl | good god, that's actually used? :) | 16:03 |
| lkcl | ok you did it alrady | 16:04 |
| lkcl | whew | 16:04 |
| lkcl | yes this is a weird one because ISACaller drops all the XYZ-Form.{opcodes} into the namespace of the function, automatically | 16:04 |
| lkcl | so the fact that target_addr was not used is irrelevant | 16:05 |
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| ghostmansd | Basically attracted my attention only because I printed all entries found in mdwn | 16:12 |
| ghostmansd | Nothing's broken, but still, for consistency's sake... | 16:12 |
| ghostmansd | Recent updates: https://bugs.libre-soc.org/show_bug.cgi?id=919#c1 | 16:18 |
| lkcl | this would be really *really* useful directly inside ISACaller, which is rather hamstrung. | 16:23 |
| lkcl | ghostmansd, are you good to do (right now) an addition to the RC Enum? | 16:26 |
| lkcl | to add RC.RC_ONLY? | 16:26 |
| lkcl | or RC.RC_NO_OE? | 16:26 |
| ghostmansd | What'd it mean? addis.? | 16:26 |
| ghostmansd | I mean, what are the cases where it's useful? | 16:27 |
| lkcl | there's an entire list of instructions that need their CSV files to be "RC-only" | 16:27 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=919#c3 | 16:27 |
| ghostmansd | And how would the disassembly benefit? | 16:27 |
| lkcl | it would not make the mistake of reading bit 30 by accident and creating a mullhwo instruction for example | 16:27 |
| lkcl | which does not exist | 16:28 |
| lkcl | and ternlogi is a real basket-case because bit 30 (normally allocated to OE) is part of the XO opcode | 16:28 |
| ghostmansd | Hm. IIRC 'o' is present in instruction name. | 16:28 |
| ghostmansd | That is, we have two entries in mdwn in such cases. | 16:29 |
| lkcl | ok if you look at power_enums.py class RC | 16:29 |
| lkcl | class RC(Enum): | 16:29 |
| lkcl | NONE = 0 | 16:29 |
| lkcl | ONE = 1 | 16:29 |
| lkcl | RC = 2 | 16:29 |
| ghostmansd | If you mean stuff like addo | 16:29 |
| lkcl | the column *only* has RC but not OE | 16:29 |
| lkcl | this is a hangover from microwatt | 16:29 |
| ghostmansd | Yes, sure. Why RC should consider OE? | 16:29 |
| ghostmansd | These are different beasts to me. | 16:29 |
| lkcl | because that's what they did in microwatt | 16:29 |
| lkcl | they coded "RC" to mean "consider RC **AND** OE" | 16:30 |
| ghostmansd | Holy fuck | 16:30 |
| ghostmansd | But this doesn't look right | 16:30 |
| lkcl | "oh and make some exceptions which you can see in that list exts* cntlz mulhw mulhd etc etc etc | 16:30 |
| lkcl | to "fix" that - properly - we need an RC_ONLY=3 in class RC | 16:30 |
| lkcl | really, we should change *both* names, so as to make damn sure that errors occur | 16:31 |
| lkcl | class RC(Enum): | 16:31 |
| lkcl | NONE = 0 | 16:31 |
| lkcl | ONE = 1 | 16:31 |
| lkcl | RC_OE = 2 # includes OE | 16:32 |
| lkcl | RC_ONLY = 3 # does not include OE | 16:32 |
| lkcl | you good with that? | 16:32 |
| ghostmansd | OK, what'd be the matching pattern here? https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=fd9439bb102b49c8d20c4233131e459d57dadac3;hb=7ccf725d657341da5a1ea4e18689f4827b34447c#l849 | 16:32 |
| * lkcl nom, nom, nom... | 16:32 | |
| lkcl | that would change to | 16:32 |
| lkcl | if record.rc not in [RC.RC_OE, RC.RC_ONLY]: | 16:32 |
| lkcl | and then there would correspondingly be an OE_match function | 16:33 |
| ghostmansd | So we'll handle two cases, RC_OE (Rc and OE) and RC_ONLY (only RC)? | 16:33 |
| lkcl | if record.rc is not RC.RC_OE | 16:33 |
| lkcl | yes | 16:33 |
| ghostmansd | and not NONE | 16:33 |
| lkcl | err... yes? :) | 16:34 |
| ghostmansd | if rc in (RC.NONE, RC.ONE): return False | 16:34 |
| ghostmansd | OK ping me when you update this bit | 16:34 |
| ghostmansd | I'd keep RC as RC, not RC_ONLY | 16:35 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=refs/heads/rc_only | 16:35 |
| lkcl | let's work in the same branch | 16:35 |
| lkcl | i've pushed that one change first | 16:35 |
| lkcl | and will start on power_decoder2.py | 16:35 |
| lkcl | on DecodeRC and DecodeOE | 16:35 |
| ghostmansd | Also, RC.RC_OE is strange... we have RC enum, but have OE member there... | 16:35 |
| lkcl | sigh yes i know | 16:36 |
| lkcl | but it is better than trying to add a separate column | 16:36 |
| ghostmansd | Maybe call it kinda like Flags or something agnostic? | 16:36 |
| ghostmansd | No-no, I mean the enum name | 16:36 |
| lkcl | which will hit literally every... ah yes | 16:36 |
| lkcl | ok | 16:36 |
| ghostmansd | I'm terrible at naming | 16:36 |
| lkcl | so am i :) | 16:36 |
| ghostmansd | class MicrowattRcSucks(_enum.Enum): YES_WE_DO_HAVE_OE_AND_RC = 0 | 16:37 |
| lkcl | haha | 16:37 |
| ghostmansd | Still, I'd think about less Rc-centric name | 16:37 |
| lkcl | done - i called it FLAGS for now | 16:37 |
| lkcl | it's a good choice because it causes errors | 16:37 |
| lkcl | meaning a *full* code review is needed | 16:38 |
| ghostmansd | Fuck fuck fuck | 16:39 |
| ghostmansd | They have _both_ Rc and RC fields | 16:39 |
| lkcl | what d'ya'do nooow | 16:39 |
| lkcl | uh-huhn :) | 16:40 |
| ghostmansd | Seriously, who was drunk? | 16:40 |
| lkcl | RC is the register (GPR) like, RA RB RC RT RS | 16:40 |
| lkcl | there is actually a reason why it's Rc. something like... Result condition | 16:40 |
| ghostmansd | Yeah but still, why not call it like RcBit, at least | 16:40 |
| lkcl | that's 5 letters when 2 will do :) | 16:41 |
| ghostmansd | Things that differ by case... nothing worse. | 16:41 |
| ghostmansd | Does OE also go into Condition Register? | 16:41 |
| lkcl | no - and that's the whole point. | 16:41 |
| lkcl | OE is bit *30* | 16:42 |
| lkcl | Rc is bit *31* | 16:42 |
| ghostmansd | Nope I mean the name of the register itself | 16:42 |
| ghostmansd | 2.3.1 | 16:42 |
| ghostmansd | pg 60 | 16:42 |
| lkcl | 1 sec | 16:42 |
| ghostmansd | assuming v3.1B | 16:42 |
| lkcl | zoom zoom zoom... | 16:42 |
| ghostmansd | Maybe we should call enum CRBits, then? | 16:43 |
| lkcl | those are *also* different. | 16:43 |
| lkcl | the Rc flag indicates *that* you should update a CR Field | 16:43 |
| ghostmansd | Fuck yeah | 16:44 |
| lkcl | for GPR operations that is CR0 | 16:44 |
| lkcl | for FPR operations it is CR1 | 16:44 |
| lkcl | and for VSX operations CR6 | 16:44 |
| lkcl | (!) | 16:44 |
| ghostmansd | It's FP exception register | 16:44 |
| lkcl | has your brain melted yet? | 16:44 |
| ghostmansd | OV and SO | 16:44 |
| lkcl | that's *even another* flag :) | 16:44 |
| lkcl | called FPSCR i think | 16:44 |
| lkcl | and that's *yet another* one - XER | 16:44 |
| lkcl | XER.OV | 16:44 |
| lkcl | XER.SO | 16:44 |
| lkcl | there is actually a reason for all this btw | 16:45 |
| lkcl | RISC-V - which has none of it - is absolutely fucked | 16:45 |
| lkcl | example: MIPS (which also doesn't have these Condition Codes) has to use **TEN** MIPS instructions to emulate a single x86 branch | 16:45 |
| lkcl | (!!) | 16:45 |
| ghostmansd | Holy cow | 16:46 |
| lkcl | yes | 16:46 |
| lkcl | and RISC-V is in the same mess. | 16:46 |
| ghostmansd | how about RegBits name? | 16:46 |
| lkcl | i just called it FLAGS for now | 16:46 |
| ghostmansd | FLAGS is waaaay too broad | 16:46 |
| lkcl | the name can change later, i want to hit the... true... | 16:46 |
| ghostmansd | e.g. PPC records do also have flags (e.g. lk) | 16:46 |
| lkcl | then i'm tempted to just call it RCOE for now | 16:46 |
| ghostmansd | if "lk" in ppc.flags | 16:47 |
| ghostmansd | Hm... This might do the trick. | 16:47 |
| ghostmansd | OK let's leave it to strangers who see this code to blame us later. | 16:47 |
| lkcl | haha | 16:47 |
| lkcl | done | 16:47 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=refs/heads/rc_only | 16:47 |
| lkcl | power_enums.py done | 16:48 |
| lkcl | power_decoder.py done | 16:48 |
| lkcl | power_decoder2.py done | 16:48 |
| lkcl | renamed in power_insns.py done | 16:49 |
| lkcl | (not added the missing case(s) though) | 16:49 |
| lkcl | whoops had to add the missing case name | 16:51 |
| lkcl | pushed | 16:51 |
| lkcl | ahh frick | 16:51 |
| lkcl | case RC currently does not exist any more in the CSV files, doh | 16:51 |
| lkcl | frick frick frick that means hitting all the csv files which i wanted to avoid, renaming RC to "RC_OE" | 16:52 |
| lkcl | ah well | 16:52 |
| lkcl | fuckit might as well | 16:52 |
| lkcl | arse feck no can't do that | 16:53 |
| lkcl | git pull | 16:54 |
| lkcl | so that's | 16:55 |
| lkcl | class RCOE(Enum): | 16:55 |
| lkcl | NONE = 0 | 16:55 |
| lkcl | ONE = 1 | 16:55 |
| lkcl | RC = 2 # includes OE | 16:55 |
| lkcl | RC_ONLY = 3 # does not include OE | 16:55 |
| lkcl | where (2) is for compatibility to avoid a massive hit on the CSV files, renaming absolutely every sodding line ,RC,0,fmsub,A | 16:55 |
| lkcl | to ,RC_ONLY,0,.... | 16:55 |
| lkcl | deep breath, deep breath | 16:56 |
| lkcl | dang this might turn out to be a lot easier than i was nervous about | 16:58 |
| lkcl | no test_caller errors so far | 16:59 |
| * lkcl might as well run the whole lot | 17:00 | |
| lkcl | and in the meantime edit the CSV files | 17:00 |
| lkcl | ghostmansd, i found another op with a pair of switch/case entries | 17:02 |
| lkcl | 0b1101111010,SHIFT_ROT,OP_EXTSWSLI,N | 17:02 |
| lkcl | 0b1101111011,SHIFT_ROT,OP_EXTSWSLI,N | 17:02 |
| ghostmansd | Yeah IIRC I haven't handle it yet | 17:02 |
| lkcl | i'll make that a single entry | 17:03 |
| lkcl | because otherwise you end up only matching the [overwriting] one pattern | 17:03 |
| ghostmansd | ...or did I?... | 17:03 |
| ghostmansd | let me check | 17:03 |
| lkcl | oh... err... arg. the entire csv file - minor_31.csv - has to convert to patterns, it is currently binary. | 17:04 |
| lkcl | argh | 17:04 |
| lkcl | i'm not doing that | 17:04 |
| ghostmansd | eeeehm | 17:05 |
| ghostmansd | openpower/isatables/RM-2P-1S1D.csv | 17:05 |
| ghostmansd | This has _completely_ duplicated entries | 17:05 |
| ghostmansd | I guess it was automatic, eh? | 17:06 |
| lkcl | yyep | 17:06 |
| ghostmansd | Perhaps we should filter out duplicates | 17:06 |
| lkcl | it'll have duplicate entries because it matches against multiple thingies. multiple instructions | 17:06 |
| lkcl | probably | 17:06 |
| lkcl | btw "stwcx." can *only* have "." at the end, you know that, right? | 17:07 |
| ghostmansd | lkcl you'll be surprized | 17:09 |
| ghostmansd | at least I was | 17:09 |
| lkcl | daaang i'm finding a whooole stack of bugs | 17:09 |
| ghostmansd | does extswsli have dotted version? | 17:09 |
| lkcl | operations that should have never been just "RC" in the CSV files | 17:09 |
| lkcl | yyep. | 17:10 |
| ghostmansd | because it appears it it does | 17:10 |
| lkcl | but not an OE=1 version | 17:10 |
| ghostmansd | and, well, considering different patterns... | 17:10 |
| ghostmansd | it makes 4 instructions, eh? | 17:10 |
| lkcl | extswsli is now an RC_ONLY in the CSV | 17:10 |
| lkcl | sigh yes | 17:10 |
| ghostmansd | Fuck. | 17:10 |
| * lkcl manic laughter | 17:11 | |
| lkcl | f*****g fp operations are all RC as well | 17:12 |
| lkcl | ah-ha | 17:12 |
| lkcl | ahahahaahahhah | 17:12 |
| lkcl | ok got a batch ready, just waiting for unit tests to run... done | 17:13 |
| lkcl | ok done, pushed | 17:16 |
| lkcl | now comes the "risky" part (for me) - removing the case statement in power_decoder2.py DecodeOE | 17:17 |
| lkcl | everything *should* still run | 17:17 |
| *** octavius <octavius!~octavius@127.125.93.209.dyn.plus.net> has joined #libre-soc | 17:17 | |
| lkcl | ya know... in some ways this RCOE flag is a duplicate of what's in the mdwn. | 17:19 |
| lkcl | (Rc=1, OE=1) | 17:20 |
| lkcl | but let's not go there right just now | 17:20 |
| * lkcl restarted all test_caller*.py | 17:21 | |
| lkcl | with now "listening" to the RCOE.RC_ONLY flag back in power_decoder2.DecodeOE | 17:21 |
| ghostmansd | 0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS, | 17:22 |
| ghostmansd | 0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS, | 17:22 |
| ghostmansd | Why couldn't we have pattern 110111101-? | 17:22 |
| lkcl | yep they're identical except for the op | 17:22 |
| lkcl | because you have to change the *entire* minor_31.csv in one hit | 17:22 |
| lkcl | and i don't want to do that in this branch | 17:23 |
| ghostmansd | My point is, this should solve the issue with handling instructions that have multiple opcodes but otherwise are the same. | 17:24 |
| ghostmansd | Without introducing stuff like "list of opcodes" | 17:24 |
| lkcl | yeeEes... but until the list-of-opcodes (or an amalgamation function written) i can't do svshape2 | 17:25 |
| lkcl | or i can but what you're doing will break | 17:25 |
| ghostmansd | OK, alternative suggestion | 17:25 |
| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=fd9439bb102b49c8d20c4233131e459d57dadac3;hb=7ccf725d657341da5a1ea4e18689f4827b34447c#l128 | 17:25 |
| ghostmansd | We have PatternOpcode | 17:25 |
| ghostmansd | used for stuff like 0-11-011 | 17:26 |
| ghostmansd | We could perhaps have a constructor or subclass of it | 17:26 |
| ghostmansd | Which takes several "fixed" opcodes | 17:26 |
| lkcl | yes. | 17:26 |
| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=fd9439bb102b49c8d20c4233131e459d57dadac3;hb=7ccf725d657341da5a1ea4e18689f4827b34447c#l121 | 17:26 |
| lkcl | i think i know what you're going to say | 17:26 |
| ghostmansd | ...and then builds such PatternOpcode | 17:26 |
| lkcl | yes. | 17:26 |
| lkcl | it's actually really easy to do | 17:27 |
| ghostmansd | Length of fields is the same... | 17:27 |
| lkcl | for i in range(32) | 17:27 |
| lkcl | bit = 1<<i | 17:27 |
| ghostmansd | Not really 32 | 17:27 |
| ghostmansd | But yes | 17:27 |
| ghostmansd | Well 32 would also do the trick | 17:27 |
| lkcl | for pattern in list_of_patterns: | 17:27 |
| lkcl | if bit same in all patterns: | 17:27 |
| lkcl | result[bit] = 1 | 17:27 |
| lkcl | mask[bit] = 1 | 17:28 |
| lkcl | sorry | 17:28 |
| ghostmansd | YeahNope | 17:28 |
| lkcl | result[bit] = incoming[bit] | 17:28 |
| ghostmansd | Hell L-)] | 17:28 |
| lkcl | :) | 17:28 |
| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=fd9439bb102b49c8d20c4233131e459d57dadac3;hb=7ccf725d657341da5a1ea4e18689f4827b34447c#l75 | 17:28 |
| lkcl | you get the idea | 17:28 |
| ghostmansd | OK, kinda similar to what's going on here for mask | 17:28 |
| ghostmansd | But this time for multiple opcodes in one go | 17:28 |
| lkcl | yes. | 17:28 |
| ghostmansd | OK I'll think how to handle it better | 17:29 |
| ghostmansd | I think I'll be able to complete it soon | 17:29 |
| lkcl | it would work well because it means no need to hit all the CSV files with a new colummn | 17:29 |
| lkcl | awesome | 17:29 |
| ghostmansd | Yeah | 17:29 |
| lkcl | and we can stop removing the bloody duplicates, too :) | 17:29 |
| * lkcl afk for a bit, need to get up. tests still running in rc_only branch | 17:30 | |
| lkcl | dang loadavg 25... | 17:30 |
| ghostmansd | OK, so, considering two integer opcodes, A and B. If A[N] == B[N], what'd be VALUE[N] and MASK[N]? What if A[N] != B[N]? | 17:36 |
| ghostmansd | I guess if not equal, this is -, right? | 17:37 |
| ghostmansd | And, if equal, this is the bit value? | 17:37 |
| lkcl | yes. | 17:44 |
| lkcl | if "-" then it is still "-" | 17:44 |
| lkcl | if not equal then it is also "-" | 17:44 |
| lkcl | only those bits that *all* match go into the thing | 17:44 |
| lkcl | ah | 17:44 |
| lkcl | i know | 17:44 |
| lkcl | first_pattern = list_of_patterns.pop(-1) | 17:45 |
| lkcl | for pattern in list_of_patterns: | 17:45 |
| lkcl | if first_pattern[bit] != pattern[bit]: | 17:45 |
| lkcl | mask[bit] = 0; continue | 17:45 |
| lkcl | mask[bit] = 1 | 17:45 |
| lkcl | result[bit] = first_pattern[bit] | 17:46 |
| lkcl | that's it | 17:46 |
| lkcl | dang unit tests passed | 17:46 |
| * lkcl re-running test_issuer.py | 17:46 | |
| ghostmansd | To me it looks strange that the first opcode is somehow "special". | 18:09 |
| ghostmansd | I'm thinking of a bit different approach which applies the same operation in chain... | 18:09 |
| ghostmansd | Stay tuned. | 18:09 |
| lkcl | ack | 18:11 |
| lkcl | i missed rwlin* (OP_RLCR) so am re-running test_issuer.py nosvp64 shiftrot | 18:12 |
| ghostmansd | OK, good news is, at so called "PPC database", we have these entries separated | 18:17 |
| ghostmansd | That is, we end up with say 2 records both named extswsli | 18:18 |
| lkcl | that's a good start | 18:18 |
| * lkcl shiftrot error gone | 18:18 | |
| ghostmansd | I really like dataclasses: they generated the __eq__ and __hash__ for us so that if even a single entry differs these are different | 18:18 |
| lkcl | oh, ah, err... | 18:19 |
| ghostmansd | And I luckily stored these dataclasses of PPC records in set | 18:19 |
| lkcl | i meant to mention | 18:19 |
| * lkcl sheepish | 18:19 | |
| ghostmansd | And, well, it found the opcodes to be different | 18:19 |
| lkcl | you know when an early version you had a list of fields as a dictionary? | 18:19 |
| lkcl | oh that's good, what was it? which ones? i need to check them | 18:19 |
| ghostmansd | PPCRecord(opcode=IntegerOpcode(value=0x0000037b, mask=0x0000037b), comment='extswsli', flags=Flags({'BR', 'rsrv', 'inv A', 'inv out', 'sgn', 'lk', 'cry out', 'sgl pipe', 'sgn ext', '32b'}), comment2='', function=<Function.SHIFT_ROT: (1 << 3)>, intop=<MicrOp.OP_EXTSWSLI: 32>, in1=<In1Sel.NONE: 0>, in2=<In2Sel.CONST_SH: 10>, in3=<In3Sel.RS: 1>, out=<OutSel.RA: 2>, cr_in=<CRInSel.NONE: 0>, cr_out=<CROutSel.CR0: 1>, cry_in=<Cr | 18:20 |
| ghostmansd | yIn.ZERO: 0>, ldst_len=<LDSTLen.NONE: 0>, upd=<LDSTMode.NONE: 0>, rc=<RC.RC: 2>, form=<Form.XS: 16>, conditions='', unofficial=False) | 18:20 |
| ghostmansd | PPCRecord(opcode=IntegerOpcode(value=0x0000037a, mask=0x0000037a), comment='extswsli', flags=Flags({'BR', 'rsrv', 'inv A', 'inv out', 'sgn', 'lk', 'cry out', 'sgl pipe', 'sgn ext', '32b'}), comment2='', function=<Function.SHIFT_ROT: (1 << 3)>, intop=<MicrOp.OP_EXTSWSLI: 32>, in1=<In1Sel.NONE: 0>, in2=<In2Sel.CONST_SH: 10>, in3=<In3Sel.RS: 1>, out=<OutSel.RA: 2>, cr_in=<CRInSel.NONE: 0>, cr_out=<CROutSel.CR0: 1>, cry_in=<Cr | 18:20 |
| ghostmansd | yIn.ZERO: 0>, ldst_len=<LDSTLen.NONE: 0>, upd=<LDSTMode.NONE: 0>, rc=<RC.RC: 2>, form=<Form.XS: 16>, conditions='', unofficial=False | 18:20 |
| ghostmansd | extswsli | 18:20 |
| lkcl | extswsli... 1 sec... | 18:20 |
| ghostmansd | Corresponds to these | 18:20 |
| ghostmansd | 0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS, | 18:20 |
| ghostmansd | 0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS, | 18:20 |
| lkcl | those aren't different | 18:21 |
| ghostmansd | They are | 18:21 |
| ghostmansd | check opcodes | 18:21 |
| lkcl | where? | 18:21 |
| lkcl | yes? | 18:21 |
| lkcl | that's "expected" | 18:21 |
| ghostmansd | 0b1101111010 vs 0b1101111011 | 18:21 |
| ghostmansd | Yeah | 18:21 |
| lkcl | (as in, we expect them to be different) | 18:21 |
| ghostmansd | I mean that the code could have dropped one entry | 18:21 |
| ghostmansd | By mistake or whatever | 18:21 |
| ghostmansd | But, due to the fact these are represented as dataclasses | 18:22 |
| ghostmansd | not some dict grouped by name... | 18:22 |
| lkcl | because this was originally designed for naive switch case-statements (multiple of, potentially, doing the same thing) | 18:22 |
| ghostmansd | ...this works | 18:22 |
| lkcl | sigh yes | 18:22 |
| ghostmansd | So this is a good start | 18:22 |
| ghostmansd | I worried I was collecting these by name | 18:22 |
| ghostmansd | Or, well, comparing, at least | 18:22 |
| ghostmansd | But not | 18:22 |
| ghostmansd | I compare the whole entries | 18:22 |
| ghostmansd | So neither entry is missed | 18:22 |
| ghostmansd | And we simply have to merge entries with same name and different opcodes into a single entity | 18:23 |
| ghostmansd | With a pattern opcode | 18:23 |
| ghostmansd | generated on the fly | 18:23 |
| lkcl | ta-daaa | 18:26 |
| lkcl | so, ah, a reminder of the sheepish-thing i forgot to say | 18:26 |
| lkcl | you know how we have fields.text for 32-bit ops? | 18:26 |
| lkcl | and how Power ISA v3.1 64-bit prefix format is also done the same way in the Power ISA v3.1 doc? | 18:26 |
| lkcl | um | 18:26 |
| lkcl | it occurred to me that the entirety of SVP64 really has to be done the same way - as a (new) fields_svp64.txt file | 18:27 |
| lkcl | um | 18:27 |
| lkcl | i can hear you banging your head on the keyboard from here... | 18:27 |
| ghostmansd | Well practically speaking yes :-) | 18:27 |
| ghostmansd | Cannot it wait until I'm done with objdump at least? :-) | 18:28 |
| ghostmansd | Fuck the whole thing is also complicated by the fact that some entries in PPC database have _multiple_ names | 18:29 |
| ghostmansd | Sigh | 18:29 |
| ghostmansd | OK, never surrender, eh? | 18:29 |
| ghostmansd | _collections.defaultdict(lambda: _collections.defaultdict(set)) | 18:33 |
| ghostmansd | Anybody stumbling at this code would think I'm a fucking pervert | 18:33 |
| ghostmansd | a default dict of default dict of sets | 18:33 |
| lkcl | of course. | 18:34 |
| lkcl | it is a long-term thing | 18:34 |
| lkcl | for which we can plan a decent budget | 18:35 |
| lkcl | but... it's like... why the bloody hell didn't that occur to me like.... weeks ago | 18:35 |
| lkcl | ok i'm happy with the rc_only branch | 18:40 |
| lkcl | (tests, power_decoder.py etc) | 18:40 |
| lkcl | what do i need to run to check s...tuff breaks? | 18:41 |
| lkcl | or shall i just cut it over to master? | 18:41 |
| ghostmansd[m] | You can cut it; I'll handle power_insn changes, and check pysvp64dis | 18:56 |
| ghostmansd[m] | Eventually I will do tests for pysvp64dis, too | 18:57 |
| ghostmansd[m] | But I'd like to land there after binutils. First, there are time concerns; second... Who knows, perhaps we could have some tests for them together? | 18:57 |
| ghostmansd[m] | I've been thinking that asm tests could use the same input, at least. Not sure how to handle it better, though, due to different repos. | 18:58 |
| ghostmansd[m] | Anyway timewise I cannot afford such a luxury; plus, things still evolve. | 18:59 |
| lkcl | ok | 19:01 |
| lkcl | indeed | 19:01 |
| lkcl | done | 19:02 |
| ghostmansd | lkcl, can we have a pathological situation when not only opcode differ, but other fields, too? | 19:11 |
| ghostmansd | I'm asking since I have no better means to group instructions other than by opcode or name. | 19:11 |
| ghostmansd | But, if we have several entries for the same name (or, well, comment), with different opcodes AND different other fields... | 19:12 |
| ghostmansd | ...I don't know how to rule this out. These should be different instructions, then, | 19:12 |
| ghostmansd | I'm thinking of raising the exception, if I meet such bastards. Thoughts? | 19:12 |
| ghostmansd | Here's the exhaustive (if I'm not mistaken) bastards list: extswsli isel mulhd mulhdu mulhw mulhwu sradi | 19:25 |
| lkcl | no absolutely not - that's a hard error | 19:57 |
| lkcl | under no circumstances should the fields be different for the same instruction name | 19:58 |
| lkcl | that list sounds about right | 19:58 |
| lkcl | most of those can be resolved to single-entries (eventually) by first doing the "convert-the-entire-file-to-pattern" trick | 19:59 |
| lkcl | but let's use them all as a test of the pattern-matching | 19:59 |
| lkcl | octavius, ping you should have received payment, do check your bank account and update the bugreports | 20:05 |
| lkcl | programmerjake, likewise, payments went out yesterday | 20:07 |
| programmerjake | didn't show up in my bank yet...they're kinda slow | 20:12 |
| lkcl | EU-US transfer, yes. | 20:15 |
| lkcl | EU/UK it'll be by CHAPS - pretty much instant | 20:15 |
| ghostmansd | extswsli RA,RS,SH (Rc=0) | 20:46 |
| ghostmansd | Everything's great, but you know what? The listing below mentions sh in lowercase. | 20:47 |
| ghostmansd | # 1.6.15 XS-FORM | 20:47 |
| ghostmansd | |0 |6 |11 |16 |21 |30|31 | | 20:47 |
| ghostmansd | | PO | RS | RA | sh | XO |sh|Rc | | 20:47 |
| ghostmansd | pg 142 of 3.1B | 20:48 |
| ghostmansd | For fuck's sake, I had to check into this for about an half an hour until I realized that they differ only by the _case_ | 20:48 |
| ghostmansd | So yeah, extswsli is marked as XS-form | 20:49 |
| ghostmansd | but has SH argument | 20:49 |
| ghostmansd | and there's no SH operand, only _sh_, lowercase, donnerwetter! | 20:49 |
| ghostmansd | Obviously it should have been uppercase | 20:49 |
| ghostmansd | Rationale: | 20:50 |
| ghostmansd | sh (30,16:20) | 20:50 |
| ghostmansd | SH (16:20) | 20:51 |
| ghostmansd | lowercase sh has only one span, and that includes bit 30 | 20:51 |
| ghostmansd | oh well | 20:51 |
| ghostmansd | nope, it should be lowercase | 20:51 |
| programmerjake | the latest in crazy usb standards naming: usb4 version 2.0, makes me wonder how long it'll be for them to have version UsB70.79.79.76 ("FOOL" in ascii) | 20:51 |
| ghostmansd | |0 |6 |11 |16 |21 |30|31 | | 20:52 |
| ghostmansd | | PO | RS | RA | sh | XO |sh|Rc | | 20:52 |
| ghostmansd | Yes indeed, lowercase, bit 30 is also occupied | 20:52 |
| ghostmansd | yes this change makes it work | 20:54 |
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| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=c09ca5a0410f7c0e1705c7eab36bab0564d0d7d3 | 20:55 |
| ghostmansd | ^ the change for extswsli operands | 20:55 |
| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=c1e2a856aa04e874bbe9d2c948bf828f4beda2af | 20:56 |
| ghostmansd | ^ support opcodes merging | 20:56 |
| ghostmansd | too tired, will check your remarks later | 20:56 |
| programmerjake | a bunch of import errors in tests in CI: https://salsa.debian.org/Kazan-team/mirrors/openpower-isa/-/jobs/3174458#L6906 | 20:59 |
| programmerjake | ImportError: cannot import name 'RC' from 'openpower.decoder.power_enums' (/builds/Kazan-team/mirrors/openpower-isa/src/openpower/decoder/power_enums.py) | 20:59 |
| ghostmansd[m] | lkcl, I would like to raise an errand to OPF | 20:59 |
| ghostmansd[m] | Is it doable? This is second error I spot, the previous one with target_addr, which you raised first. :-) | 21:00 |
| programmerjake | src/openpower/decoder/test/test_power_decoder2.py:15 | 21:00 |
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| lkcl | ghostmansd, yes i can do that. | 21:28 |
| lkcl | or, now you can raise an External RFC / minor correction, yourself, if you like | 21:28 |
| lkcl | https://openpower.foundation/isarfc/ | 21:29 |
| lkcl | you want radio-button (1) | 21:29 |
| lkcl | i will raise the bugreport internally anyway, i'll be fascinated to see what happens | 21:29 |
| programmerjake | since the spec. source isn't yet public, i'd assume you don't need a git patch, and should just describe it or something | 21:35 |
| lkcl | probably. or just attach the libresoc git diff :) | 21:37 |
| lkcl | ghostmansd, https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;hb=HEAD#l795 | 21:47 |
| programmerjake | lkcl: imho you should try to ensure specific git commits are in gitweb urls, rather than linking to HEAD, because that way the urls still work when reading irc again later | 21:59 |
| octavius | lkcl, payment did come through, updated the bugs and wiki page | 22:25 |
| octavius | Also making progress on the manual pinmux demo (src/spec/stage2.py). Have tests for very dumb UART/I2C/GPIO (no logic, just signal transitions), to test the connectivity between the periph side and the pads. The pad names are now a parameter (as a list), however the code itself is not parametrised yet. Although it's starting to make more sense. Also haven't done the pretty gtkwave file yet | 22:53 |
| octavius | https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/stage2.py | 22:55 |
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| octavius | currently I'm thinking of the dict/indexing. The pads dict contains the pads (accessible by user-specified name) | 22:59 |
| octavius | pads['N1'].i/o/oe | 23:00 |
| octavius | but we want the pad dict to point to the peripherals? | 23:00 |
| octavius | for example, pads['N1']['bank0'].i/o/e | 23:01 |
| octavius | although this doesn't include the peripheral information | 23:01 |
| octavius | I guess each 'pad' entry could contain the dict of bank0-3 and the actual pad Records | 23:02 |
| octavius | pads['N1'] = {'bank0':Record,... 'bank3':Record, 'pad':Record} | 23:03 |
| octavius | I'll continue tomorrow, gn | 23:05 |
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