Saturday, 2022-09-24

programmerjakegot pcdec. to work! will commit after all tests pass01:15
lkclahh brilliant01:18
programmerjakeall tests pass! thx for fixing all the other tests :)01:22
lkclvery cool instruction/idea01:29
lkclbits-unused feeds back. worked that out01:29
lkclwhat happens if there are more bytes being produced than there are bits in input?01:30
lkclthat's a different type of overflow condition from "there are greater than 6-bit-encodings", right?01:30
programmerjakethat's impossible, it will notice there's no input bits so it'll just stop there, leaving the rest the bytes in RT set to 0 (means unused)01:30
lkclRT=0 is not "the output was all zero-bytes"?01:31
programmerjakeRT=0 is "there was no output bytes" since output bytes can't be zero.01:32
lkclngggh... these aren't actual "data bytes", they're indices-into-the-table-of-output, aren't they?01:33
lkcl(something like that)01:33
programmerjakethey're decoded symbols packed into 1 per byte, symbols can be 1-bit to as-many-as-you-please. pcdec. only handles symbols up to 5-bits (not 6-bits, that was an error)01:34
programmerjakesymbols are encoded by taking the symbol's bits, packing them from LSB to MSB, then adding a 1-bit, then filling the rest of the byte with zeros01:35
programmerjakeencoded into bytes in RT ^01:35
programmerjakeso their kinda indices into the table of all possible outputs, but rearranged to just be LSB0 indices into the corresponding 1-bit in tree01:36
lkclreally want to see what happens on sv.pcdec.01:38
lkcland if /ff mode helps01:38
programmerjakeff mode is the only way it can be vectorized at all...01:39
lkcl /vli mode btw is only possible with testing *just* "eq" bit (ne/eq the only two options)01:40
programmerjakeicr what vli stands for...01:40
lkcltruncates VL *inclusive*01:40
lkclif the test fails VL is truncated normally to *exclude* the failing element01:41
programmerjakeyeah, we'll want to include the last element01:41
lkclthen you can't use /ff=lt or /ff=so01:42
lkclit has to be /ff=RC1/vli which i'll write tomorrow01:42
programmerjakeI'll move the "output-empty" to lt, and have eq be "we hit any stopping condition"01:42
programmerjakenext week, when I'm working on it again01:43
lkclalso i didn't foresee having this applied to "only-Rc=1" instructions01:43
lkclRC1 mode was only originally designed for instructions that don't have an Rc=1 mode01:43
lkcli'll have to do an XOR of the hard-coded-Rc=1 (csv rc column == 'ONE') /ff=RC1 flag01:44
programmerjakeuuh, couldn't it just be sv.pcdec./vli/ff=eq?01:44
lkclit's a tri-mode not a dual-mode01:45
lkcl(one flag==1 enables/activates another flag)01:46
lkcl(i.e. the 2nd flag is *ignored* if the 1st flag == 0)01:46
programmerjakeuuh, RC1=1 can't be used, since the spec says the results are never stored, only the CR outputs...the whole point of pcdec. is the RT output, without it it's mostly useless01:48
programmerjakeeither that or the spec is unclear01:48
programmerjake> Note that when RC1=1 the result elements are never stored, only the CR Fields.01:49
programmerjakeimho the spec should be changed to always write outputs for each element up to and including the first one that fails the data-dependent fail-first test, only elements after that one are not executed. VL being set to exclude the failing element should happen after.01:51
programmerjakethat way, an element is always fully-executed or not executed. not partially-only-writes-CR-executed01:52
programmerjakeall outputs, RT, CR, OV, etc.01:53
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lkclthat's in predicate-result mode09:25
lkclor, it's supposed to be...09:25
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ghostmansdlkcl, I believe this patch with inversion is wrong, becase it makes the wole thing extremely inconsistent.10:28
ghostmansdEither you should invert it in predicates, too, or keep it as is.10:28
ghostmansd`/ff =nl` seems to give different results than `/m=nl`10:29
lkclghostmansd, nggh, yyeah.... it means moving things in the spec though11:16
lkcland in hardware, the position of wires is not actually important11:16
ghostmansd[m]I don't understand why not keep it the way it was11:16
ghostmansd[m]Symmetrical and evident11:17
lkclbecause it was not according to the spec11:17
ghostmansd[m]You mean the order of bits?11:17
lkclwhat is symmetrical and evident in hardware is not the same as symmetrical and evident in software11:17
lkclwhether bits are *shared* between the same wires is more important11:17
ghostmansd[m]This means that there are _two_ copies of predicates, one swaps the bits and other doesn't11:18
lkclnow, if bits 19-23 were *actually* shared with predicate mask bits, that would matter11:18
lkclbit-ordering in hardware is completely meaningless as far as how they are shown in a specification11:19
lkcli know it's very weird.11:19
ghostmansd[m]Yes, extremely11:19
lkclthey only matter what they are connected to11:19
ghostmansd[m]Ok, so I do need to keep two tables of predicates11:20
ghostmansd[m]I mean binutils11:20
ghostmansd[m]Also, I think a more obvious way to show this difference would be to explicitly filling in the table11:20
ghostmansd[m]Without swaps11:20
lkcland document it11:20
ghostmansd[m]Could you do it please for pysvp64asm, while I handle binutils?11:21
ghostmansd[m]Thank you!11:21
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ghostmansdcat /tmp/test.s && SILENCELOG=true pysvp64asm /tmp/test.s /tmp/ && powerpc64le-linux-gnu-as /tmp/ -o /tmp/test.o && powerpc64le-linux-gnu-objcopy -Obinary /tmp/test.o /tmp/bin.o && pysvp64dis /tmp/bin.o11:51
ghostmansdsv.add./ff=nl/m=nl *3,*7,*1111:51
ghostmansdec 3f 50 07    sv.add./ff=ge/m=ge *r3,*r7,*r1111:51
ghostmansd15 12 01 7c11:51
ghostmansdThat's from master11:51
ghostmansdEither dis needs some tuning, or asm does the wrong thing11:51
ghostmansdlkcl ^11:51
ghostmansdalso, the comment "# decodes "Mode" in similar way to BO field (supposed to, anyway)" it somewhat misguiding :-)11:51
ghostmansdexcept for "supposed to" part, perhaps11:51
ghostmansdAh wait, I got it. ge is alias to nl.11:52
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ghostmansdlkcl, so, just to put all dots above all i's: we use the same predicates for ff/pr as for m/dm/sm, but swap the byte order for mask. Is it correct?12:13
ghostmansdTried doing this, but it didn't work. Basically all ff/pr handling is broken.12:44
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ghostmansdThe assembly is what's broken13:19
ghostmansd`sv.add./ff=ge/m=ge *r3,*r7,*r11` gives this on binutils branch: ec 3f 50 0713:20
ghostmansdOn binutils, I get this: e4 3f 50 0713:20
ghostmansdOK it seems this is mode-related. I suspect that it's again this fricking MSB0 order.13:36
ghostmansdYes it was exactly this.13:38
ghostmansdOK updated.13:42
lkclyes, have to be careful to get aliases right13:50
lkclya got there? :)13:51
lkclrebase done btw (tests passed)13:51
ghostmansdOh cool13:53
ghostmansdLuke, can we postpone updating spec on the flight at least for a while?13:53
ghostmansdIt's really complex to develop binutils when there're changes in spec or svp64asm.13:54
ghostmansdI basically have to track all four: specs, pysvp64asm, pysvp64dis and binutils.13:54
ghostmansdAnd some changes are easy to miss.13:55
ghostmansdThe addition of RS register to OutSel was one of them.13:55
ghostmansdI wouldn't even noticed it unless I had to re-generate the header and the source for a completely unrelated reason.13:55
lkclah - yeah that one was partly-cosmetic, partly-not13:56
ghostmansdI mean, it's difficult to develop further and keep up to date simultaneously.13:56
lkclthe new instruction "pcdec." is an overwrite pair (RT,RS)13:56
ghostmansdThank you!13:58
ghostmansdThe assembly part is likely totally outdated for branch modes. I guess for CRs too.13:58
ghostmansdI think it might be even outdated for pysvp64asm, the code there is so hairy with tons of variables, that I cannot even keep track of how it correlates to the spec.13:59
ghostmansdAt least disassembly is sufficiently close to the spec, speaking of how it sets bits.13:59
ghostmansdBut all these manipulations in pysvp64asm, all these if/else chains, etc., etc., they should eventually be done simpler too.14:00
lkclCR_ops haven't actually been done at all, it's simply a massive coincidence14:00
lkclyes i'd really like sv/trans/ to be updated14:01
ghostmansdWe already have tools for these, selectable int and fields, combined together, they make the code look close to spec.14:01
lkclFAIL: test_13_RC1 (__main__.SVSTATETestCase) [0:sv.add/ff=RC1]14:01
lkcl- sv.add/ff=RC1 *3,*7,*1114:01
lkcl?           ^^^14:01
lkcl+ sv.add/ff=gt *3,*7,*1114:01
ghostmansdThat's test_pysvp64dis?14:01
ghostmansdWill check.14:01
ghostmansdYeah reproducible14:02
ghostmansdI guess this is part of this inv manipulation.14:03
lkclRC1 set when it should not be... or not set14:04
ghostmansdsv.add/ff=RC1 *3,*7,*1114:05
ghostmansde9 3f 40 05    sv.add/ff=gt *r3,*r7,*r1114:05
ghostmansd14 12 01 7c14:05
ghostmansde9 3f 40 05    sv.add./ff=gt *r3,*r7,*r1114:05
ghostmansd15 12 01 7c14:05
ghostmansd`sv.add./ff=gt *3,*7,*11` is encoded the same way as `sv.add/ff=RC1 *3,*7,*11`14:06
ghostmansdsv.add./ff=gt *3,*7,*1114:06
ghostmansdsv.add/ff=RC1 *3,*7,*1114:06
ghostmansde9 3f 40 05    sv.add./ff=gt *r3,*r7,*r1114:06
ghostmansd15 12 01 7c14:06
ghostmansde9 3f 40 05    sv.add/ff=gt *r3,*r7,*r1114:06
ghostmansd14 12 01 7c14:06
lkclok yep RC1 is not being reported14:06
ghostmansdNo it would have been reported14:06
lkclsv.add/ff=RC1/vli 3,7,1114:06
lkcl0b 00 40 05    sv.add/ff=so r3,r7,r1114:06
lkcl14 5a 67 7c14:06
ghostmansdIf it had been encoded properly14:06
ghostmansdAh wait14:07
ghostmansdRc seems not to be taken into account14:07
ghostmansd14 12 01 7c vs 15 12 01 7c14:07
ghostmansdThough it was before this inv crap14:07
ghostmansd(or it silently worked)14:07
lkcl    Rc14:08
lkcl        014:08
lkcl    RM14:08
lkcl        normal: Rc=1: ffirst CR sel14:08
lkcl        RM14:08
lkcl            00000000000000000000101114:08
lkcl        RM.mode14:08
lkcl            0101114:08
lkcl            27, 28, 29, 30, 3114:08
ghostmansde9 3f 40 05    sv.add./ff=gt *r3,*r7,*r1114:08
ghostmansd    Rc14:08
ghostmansd        114:08
ghostmansd        6314:08
ghostmansdIt's taken into account14:09
ghostmansdOr, well, it's recognized14:09
ghostmansd        normal: Rc=1: ffirst CR sel14:09
ghostmansde9 3f 40 05    sv.add/ff=gt *r3,*r7,*r1114:09
ghostmansd    RM14:10
ghostmansd        normal: Rc=1: ffirst CR sel14:10
ghostmansdThis is wrong14:10
ghostmansdLooks like after that change you did you forgot to update the tables14:10
ghostmansdThe lookup is wrong14:10
ghostmansdSeems like the most rational idea14:10
lkclohh yeah14:11
lkclit should be going to.... ffrc014:11
lkcllet me just put a debug-print...14:11
ghostmansdI mean value and mask14:12
ghostmansdRc is fine14:12
ghostmansdIt's 1 for . and 0 otherwise14:12
ghostmansdIt's this damned inv change14:12
lkclsv.add/ff=RC1/vli 3,7,1114:12
lkclmatch 0b10001 0b110001 ffrc114:12
ghostmansdSo Rc is 1?14:13
ghostmansdBTW what's search?14:13
lkclno, Rc=false14:13
ghostmansdHow is it matched then?14:13
lkclah did you happen to change how Rc is done?14:14
lkcldid you remove an __bool__ function?14:14
ghostmansd    @cached_property14:14
ghostmansd    def Rc(self):14:14
ghostmansd        Rc = self.mdwn.operands["Rc"]14:14
ghostmansd        if Rc is None:14:14
ghostmansd            return False14:14
ghostmansd        return bool(Rc.value)14:14
ghostmansdThis gets SI or None14:14
ghostmansdIIRC SI has __bool__14:14
lkclurr bizarre14:15
ghostmansd1 sec14:15
ghostmansdThis gets Operand or None, sorry14:15
lkclok doing "Rc = 1 if Rc else 0"14:15
ghostmansdStill this `return bool(Rc.value)` gets SI14:15
ghostmansdI get Rc = True and Rc = False for these two instructions14:16
lkclwhich still doesn't quite work due to "|" with the other table entries14:16
lkcl            search = ((int(rm.mode) << 1) | Rc)14:16
lkclalways sets LSB of that int to 114:17
ghostmansdWhy, if it's bool?14:17
ghostmansdShouldn't it be converted to int implicitly?14:17
lkclbecause it's not actually a bool i don't think, you return a SelectableInt() *from* __bool__() is that right?14:18
lkcloh wait14:18
lkclhang on14:18
lkclmatch 0 0b10001 0b110001 ffrc114:18
ghostmansdprint(type(Rc), Rc, bin(search))14:18
ghostmansd<class 'bool'> True 0b1001114:18
ghostmansde9 3f 40 05    sv.add./ff=gt *r3,*r7,*r1114:18
ghostmansd15 12 01 7c14:18
ghostmansd<class 'bool'> False 0b1001014:18
ghostmansde9 3f 40 05    sv.add/ff=gt *r3,*r7,*r1114:18
ghostmansd14 12 01 7c14:18
lkcl                    print ("match", Rc, bin(value), bin(mask), member)14:18
lkcl1 sec14:18
lkclmatch 0 0b10110 0b10001 0b110001 ffrc114:19
lkcl                if ((value & search) == (mask & search)):14:19
lkcl                    print ("match", Rc, bin(search), bin(value), bin(mask),14:19
lkcl                                member)14:19
lkcli have that wrong, don't i?14:20
ghostmansdfirst, which instruction do you dump?14:20
lkclthat should be value & mask == search & mask14:20
ghostmansdI'd have sad valyue & mask14:20
* lkcl face-palm14:20
lkcl    RM14:20
lkcl        normal: Rc=0: ffirst z/nonz14:20
lkcl        RM14:20
lkcl            00000000000000000000101114:20
lkclall good :)14:20
* lkcl whistles14:20
lkclsv.add/ff=RC1/vli 3,7,1114:21
lkclmatch 0 0b10110 0b10000 0b110001 ffrc014:21
lkcl0b 00 40 05    sv.add/ff=RC1/vli r3,r7,r1114:21
ghostmansdsv.add./ff=gt *3,*7,*1114:21
ghostmansdsv.add/ff=RC1 *3,*7,*1114:21
ghostmansde9 3f 40 05    sv.add./ff=gt *r3,*r7,*r1114:21
ghostmansd15 12 01 7c14:21
ghostmansde9 3f 40 05    sv.add/ff=RC1 *r3,*r7,*r1114:21
ghostmansd14 12 01 7c14:21
ghostmansdThis works14:21
ghostmansdAh OK you also did this :-)14:21
ghostmansdpushed to binutils14:22
lkclwhy the hell it suddenly stopped working...14:22
lkclsorry, my mistake to fix.14:23
ghostmansdnot only yours :-)14:23
ghostmansdI also copied it to binutils14:23
ghostmansdTwo pairs of eyes are better they said14:23
ghostmansdexactly the same commit14:24
lkcltwo one-eyed kings...14:24
ghostmansdI guess I can rebase safely14:24
ghostmansdHm, I'd have written it differently14:25
ghostmansdif ((value & mask) == (search & mask)):14:25
lkclhey knock yourself out14:25
ghostmansdOK back to the binutils14:28
ghostmansdah you know what?14:28
ghostmansdif ((subtable->value & match) == (subtable->mask & match))14:28
ghostmansdI did it correctly lol14:28
lkclnggh yeah14:28
ghostmansdah no14:28
lkclhonestly i tend to guess these things14:29
lkclurrr... yeah it should also be subtable->value & subtable->mask == match & subtable-mask14:29
lkcldoh :)14:29
ghostmansdalready done :-)14:30
ghostmansdyou noticed that I had to occupy 1 bit for Rc?14:30
ghostmansdin binutils14:30
ghostmansdbecause they don't store it14:30
ghostmansdwe could check for . in the name (we already decoded it in dis), but I feel it's way to fragile14:31
ghostmansdwe already have crap like andis.14:31
ghostmansdwhere there's no andis14:31
ghostmansdSo I thought it'd be better to keep what we have in mdwn14:32
ghostmansd  uint64_t inv = svp64_insn_get_prefix_rm_ldst_imm_prrc0_inv (&svp64->insn);14:32
ghostmansd  uint64_t els = svp64_insn_get_prefix_rm_ldst_imm_prrc0_els (&svp64->insn);14:33
ghostmansd  uint64_t RC1 = svp64_insn_get_prefix_rm_ldst_imm_prrc0_RC1 (&svp64->insn);14:33
ghostmansdFeel the power of fields lol14:33
ghostmansdwhat for fuck's sake is SEA?14:34
ghostmansdShould it be /sea?14:34
ghostmansdI mean, at the point when user calls some ld/st instruction, how he affects it to set SEA?14:37
ghostmansdhow does he affect*14:37
lkclsigned effective address14:41
lkclit's for when you do elwidth overrides to below 64-bit14:41
lkclso you have a register RB which is now only 32-bit14:41
lkclit gets added to RA (64-bit)14:41
lkcldo you add 32-bit RB to 64-bit RA as signed or unsigned?14:42
lkclboth are useful14:42
lkclhence /sea14:42
lkcland yes it hasn't been added in to sv/trans/ sigh14:42
ghostmansd[m]Ok, I'll add it14:50
ghostmansd[m]To all of them14:50
ghostmansd[m]I'd be simpler to keep track14:50
ghostmansd[m]pysvp64asm, pysvp64dis and binutils14:50
lkclack leave it with you15:10
* lkcl going to try doing RC1 in ISACaller15:10
lkclactually get it working, so programmerjake has something for "sv.pcdec./ff=RC1"15:11
ghostmansdlkcl, there's (again!) contradiction between the code and the spec15:50
ghostmansdis SEA available in simple ld/st idx mode?15:50
ghostmansdFrom the spec, it is15:50
ghostmansdFrom the code, tables consider this to be part of the mask and assume bit 3 of mode to be 015:51
ghostmansdI fixed the code, cf. binutils branch. Please update the spec otherwise.15:52
ghostmansdcf. LD/ST Indexed here:
ghostmansdI think you simply did copy&paste error from LD/ST Immediate in the code15:58
ghostmansdAlso, how's setting ld/st idx stride mode is done? `sv.ldux/sea/ff=RC1 5,6,7` is the only (except for ~RC1) way I could think of. But this will lead to `sv.ldux/sea/sz r5,r6,r7`, since pysvp64asm sets only DZ field.16:14
ghostmansdAgain, this all is extremely inconsistent and confusing.16:14
ghostmansdOthewise there must be some other way to set sv_mode = 0b01 for ld/st idx. ff explicitly bans src_zero (with totally misleading comment).16:16
ghostmansd# "failfirst" modes16:16
ghostmansd            elif sv_mode == 0b01:16:16
ghostmansd                assert src_zero == 0, "dest-zero not allowed in failfirst mode"16:16
ghostmansdI'll leave this mess to you to sort out. For now only ld/st idx simple mode is supported and test for it is pushed too.16:18
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lkcl1 sec16:53
lkclermmm ermermerm...16:53
lkclSEA is *only* available in LD/ST-indexed16:54
lkcli haven't implemented SEA so you're literally the first person to look at it.16:57
lkclfail-first mode is *not* possible in LD/ST-indexed16:58
ghostmansd[m]Well, how does one set 0b01 sv_mode?17:00
ghostmansd[m]I want ld/st idx strided. It's 0b01. How can I set it? Currently the only option to set sv_mode to 0b01 is ff.17:02
ghostmansd[m]And, well, ff conflicts with ld/st idx strided.17:02
ghostmansd[m](not to mention it's not in the table at all).17:03
ghostmansd[m]If strided was the only mode to allow SEA, I'd have thought that it's /sea itself to set the mode. But it's not the case, SEA is in simple mode too.17:04
lkclit should be "/els"17:04
ghostmansd[m]Sorry, there's no bit in spec named els.17:05
ghostmansd[m]That was another guess.17:05
ghostmansd[m]If SEA is only in simple, then els will replace SEA in strided mode.17:05
lkclno, you *use* "/els" to set mode=0b0117:05
lkclsee this?17:05
lkcl                if is_ldst:17:06
lkcl                    # TODO: for now, LD/ST-indexed is ignored.17:06
lkcl                    mode |= ldst_elstride << SVP64MODE.ELS_NORMAL  # el-strided17:06
lkcli haven't added it17:06
lkcllet me sort that17:06
lkcl             elif encmode == 'els':17:08
lkcl                 ldst_elstride = 117:08
lkcl+                # in indexed mode, set sv_mode=0b0117:08
lkcl+                if is_ldst_idx:17:08
lkcl+                    sv_mode = 0b0117:08
lkcl1 sec17:08
ghostmansd[m]Keep in mind that other mode prints /els17:08
ghostmansd[m]IIRC normal mode17:08
lkclyou mean ldst-imm17:08
ghostmansd[m]Ah yes17:08
ghostmansd[m]Well anything that inherits from ElsBaseRM17:08
ghostmansd[m]Or how I called it17:08
lkclok let's add a test for it...17:09
lkclreally should have that check that RA and RB must be scalar, but hey17:10
lkclok done sv/trans/svp64.py17:20
lkclwhen LDST_IDX is detected, and "/els" is used, that's when mode=0b01 is allowed17:22
markos[       OK ] SVP64/VpxVarianceTest.OneQuarter/9 (70950 ms)17:29
markos[----------] 40 tests from SVP64/VpxVarianceTest (25578716 ms total)17:29
markos[----------] Global test environment tear-down17:29
markos[==========] 40 tests from 1 test suite ran. (25578717 ms total)17:29
markos[  PASSED  ] 40 tests.17:29
lkclmarkos, aawesome :)17:30
lkclthat took a while17:30
markosyeah, and I had to remove the 64x64 blocks and even more reduce the number of iterations, it took more than 24h and it was still doing 64x64 blocks in the morning :D17:30
markosso I'm thinking of trimming the variance tests to only include the functions I've done so far -2 more remaining but they're mostly the same stuff- and consider VP9 done and move to VP8 to a slightly more complicated function (quantize)17:31
markosis that ok with you?17:31
markoshave to be afk now, will commit the stuff so far17:32
lkclyep perfect17:32
ghostmansdlkcl, just returned to laptop. Thank you for patches, will take a look now and update binutils.18:26
ghostmansdlkcl, apparently you didn't merge binutils patches, right?18:27
ghostmansdaaah I see18:27
ghostmansdnever mind :-)18:27
ghostmansdI think this is really hacky: if sv_mode == 0b01 and is_ldst_idx:18:40
ghostmansdOther modes are somewhat "unified", except for perhaps branches.18:41
ghostmansdlkcl, I've been thinking that some specifiers should perhaps require setting mode before allowing to use them.18:43
ghostmansdNot like "collect all specifiers and potentially set the mode, then finally post-check some stuff like SEA and diagnose that the mode was not set". But, instead, "if we found /sea and mode is still not set, immediately surrender and suggest the correction".18:45
ghostmansdRationale is that this relationship is more obvious, and also makes the code a bit more linear.18:46
lkclyes that makes sense18:46
ghostmansdWhat do you think?18:46
ghostmansdOK, good!18:47
ghostmansdI have to admit that the assembly part is outdated a lot.18:47
lkclstill probably needs either a 2-pass or something18:47
ghostmansdI added zz, will add SEA and other stuff, but this will need refactoring anyway.18:47
ghostmansdI don't have time to do it in scope of disassembly.18:47
ghostmansdAnother problem is that I'd like to refactor commits in a way so that both assembly and disassembly for each specifier appears together with the tests for binutils.18:48
ghostmansdAnd this will take a lot of time and should preferably be done after we refactor our reference assembler.18:48
lkclyeah that makes sense although don't push it unnecessarily18:48
ghostmansdSo this saga is not over. :-(18:49
ghostmansdWaht do you mean by pushing unnecessarily?\18:49
ghostmansdYou mean that upstream branch? :-)18:49
ghostmansdRemoved by Alan18:49
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lkcloh were you referring to binutils?18:53
lkcli thought you mean refactor openpower-isa repo commits18:54
ghostmansdah no18:57
ghostmansdI meant binutils18:57
ghostmansdcurrently I have a lot of commits which add specifiers to assembly18:57
ghostmansdthen some commits which support these in disassembly18:58
ghostmansdon the other hand, in disassembly, we support these in per-mode fashion18:58
ghostmansd(which frankly we should do in assembly too)18:58
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ghostmansdI've walked over 38 commits (some are really huge) and synced them to some degree with pysvp64asm (SEA, els, etc.). Stuff I don't sync now includes VLi and branches: these are handled by new fields, and I'll handle them in scope of switching the whole binutils assembly to this mechanism.20:10
ghostmansdUpon disassembly, this already proved to be a perfect choice; for assembly, the only change I'd like to have is to have modes enforced (e.g. forbid SEA without /els and non-LDST-idx, allow VLi only for normal failfirst Rc=0, etc.20:12
ghostmansdTomorrow I hope to complete CR ops and branches in disassembly.20:13
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