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| Ritish | Mornin, I was trying to use the microwatt-verilator branch that you mentioned yesterday, lkcl | 07:51 |
|---|---|---|
| Ritish | But, when I run " make microwatt-verilator". It ran for a while, but later it said .config file not found | 07:52 |
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| lkcl | ghostmansd, yes good idea. what you're doing is really appreciated. the context i explained a few weeks ago may not have fully sunk in yet. i'll email you directly | 11:22 |
| lkcl | Ritish, usually under these circumstances you provide a full build log (capture of stdout/stderr). otherwise you are asking us to play the "1000 questions guessing game" | 11:23 |
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| lkcl | we also have no idea what commands you have run, or in what order, so you need to provide that information. | 11:27 |
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| ghostmansd | lkcl, it's me again with these damn CR ops. I cannot get how instruction `sv.cmp/ff=eq/vli *0, 1, *16, 0` is even possible. | 17:46 |
| ghostmansd | For the record, even the master code produces `sv.cmp/dz/ff=RC1/vli *0,1,*16,0` disassembly. | 17:47 |
| ghostmansd | src/openpower/decoder/isa/test_caller_svp64_inssort.py doesn't check it, so it just silently passes. | 17:47 |
| ghostmansd | But overall it looks that cmp et al. can only work with RC1/~RC1. | 17:47 |
| ghostmansd[m] | These CRs break everything around. | 17:52 |
| ghostmansd[m] | The code around them is a huge hack. When I try to make it work, it simply fails. | 17:54 |
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| lkcl | ghostmansd, yes, that's an illegal instruction - ff=RC1 is not in the specification | 19:56 |
| lkcl | yes, remember, i haven't had the time to implement any of it, and the extremely-rudimentary implementation showed flaws in the specification that needed correcting | 19:56 |
| lkcl | since then i have not had the time to go back and remove the illegal/incorrect instruction encodings | 19:57 |
| lkcl | sv.cmp/ff=RC1 is an illegal instruction - it is not in the specification https://libre-soc.org/openpower/sv/cr_ops/ | 19:58 |
| lkcl | this is the table | 19:58 |
| lkcl | https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/cr_ops.mdwn;h=c25b73e88c94103a861f8545ea2f773d7cbd118a;hb=f86dee196769951c8fd3cc93739f9dceb9ca7d9e#l80 | 19:58 |
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| ghostmansd | lkcl, lol, we check it test_pysvp64dis :-) | 21:55 |
| ghostmansd | For now I've just reflected the original assembler, 1:1, and left a FIXME | 21:56 |
| ghostmansd | lkcl, a question on "duplicated" operands, e.g. in stfsu | 23:35 |
| ghostmansd | d:RA,s:FRS,s:RA | 23:35 |
| ghostmansd | ^ here we have RA twice, therefore we should record this fact, and should not add RA to operands | 23:36 |
| ghostmansd | * do not add RA twice, sorry | 23:36 |
| ghostmansd | With vanilla ISA, it's clear: we don't want RA to appear twice in new fields. | 23:40 |
| ghostmansd | Do we also skip manipulations with extra2/extra3 fields? | 23:41 |
| ghostmansd | I don't quite get how it works. | 23:45 |
| ghostmansd | It seems that we modify extra2/extra3 regardless of whether the duplicate has been present. But why? Shouldn't this be omitted too? | 23:53 |
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