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| lkcl | kanzure, thx, much appreciated. | 09:55 |
|---|---|---|
| lkcl | looks like RED Semi is going ahead with a single-core first processor focussing on cryptographic acceleration | 09:56 |
| lkcl | (using libre-soc LGPLv3+ HDL) | 09:56 |
| lkcl | we're seeking commercial funding to get it into production and to finish the (LGPLv3+) HDL | 09:57 |
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| lkcl | ah. interesting. https://bugs.libre-soc.org/show_bug.cgi?id=589#c14 | 12:18 |
| lkcl | that announcement by NIST makes ascon a high-priority for investigation, like chacha20. | 12:18 |
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| lkcl | toshywoshy, ping, aware you're in ghent: bridge is down (to oftc.net) | 12:20 |
| markos | lkcl (or anyone else ftm), how can I get bugzilla to send me mail notifications when a new bug is submitted to eg. LibreSOC/Source Code component? | 12:24 |
| markos | I do get notifications when I'm added to a particular bug, but as it is, unless I browse/search the bugs I don't know what is there | 12:27 |
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| kanzure | probably a lot of money available from the ZKP people these days given all the VC activity in that space | 12:44 |
| kanzure | hardware acceleration of zero-knowledge matmult stuff would be a hit | 12:45 |
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| lkcl | markos, you subscribe to libre-soc-bugs@lists.libre-soc.org | 22:36 |
| lkcl | kanzure, the premise of the project is, "which low-level capabilities in terms of general-purpose vectorisation-looping based on general-purpose scalar instructions would result in reduced power and/or greater performance"? | 22:37 |
| lkcl | so if right at the *bottom* of the zero-knowledge-proofs stack there is a mathematical... "thing" (a standard matrix multiply) | 22:38 |
| lkcl | or if there's a basic operation (a GF2 64-bit mul/div/add) | 22:38 |
| lkcl | we can look at those, find *other places* that those same concepts (e.g. matrix-multiply-the-general-concept, e.g. GF2 arithmetic) | 22:39 |
| lkcl | and use the fact that they're used not just in one place but in multiple other places as a justification for (a) adding them and (b) proposing them to the OPF ISA WG | 22:39 |
| lkcl | counter-example: someone wrote a great Msc dissertation for chacha20 which summarised as, "if you added this totally non-generic non-useful-for-any-other-purpose instruction, you reduce chacha20 assembly instructions for RISC-V from 1,000 down to 500" | 22:41 |
| lkcl | that's an absolutely useless approach for us (but perfect for some embedded scenarios for which in general RISC-V is well-suited) | 22:41 |
| lkcl | just looking at these algorithms https://en.wikipedia.org/wiki/Zero-knowledge_proof | 22:43 |
| lkcl | are there any that have REALLY CLEAR - completely non-optimised, REALLY easy-to-read - reference implementations in at least c and preferably python as well | 22:43 |
| lkcl | that are *specifically* designed for tutorial and educational purposes? | 22:44 |
| lkcl | heavily-optimised SIMD algorithms are worse than useless for translating to SVP64 - or even reading to find out what the hell the actual algorithm does in the first place - because they're so all over the place | 22:45 |
| lkcl | we consistently and routinely find it's better to go back to the c reference implementation, containing loops such as "for (i=0;i<5;i++) { x[i] ^= y[i]; }" | 22:46 |
| lkcl | and by a not-so-coincidence that turns into TWO instructions. | 22:46 |
| lkcl | SETVL to 5 | 22:46 |
| lkcl | sv.xor (which picks up the vector length from the previous instruction) | 22:46 |
| lkcl | no pissing about with 128-bit this, 256-bit that. | 22:47 |
| lkcl | markos, you can find anything you missed (and are interested in) at the archives http://lists.libre-soc.org/pipermail/libre-soc-bugs/ | 22:47 |
| lkcl | bear in mind though that anything marked as a "specification" bug goes into libre-soc-isa. http://lists.libre-soc.org/pipermail/libre-soc-isa/ | 22:48 |
| lkcl | kanzure, bottom line we do *not* do "specific hardware macros" | 22:49 |
| lkcl | aside from anything both the NSA and CESG would *immediately* slap a weapons-grade certification on what we're doing and we'd only be able to sell the SoC with a BXPA Export License. | 22:49 |
| lkcl | by keeping things as a *general-purpose-processor* we avoid that... that... "uranium-enriched-concrete-block-with-chain-attached-round-our-legs-dropped-into-the-ocean" | 22:50 |
| lkcl | been there, dodged that bullet already, with Aspex Microelectronics, back in 2004. | 22:51 |
| kanzure | cryptographic hardware can be added as extra modules that you don't manufacture by default, w/e | 22:56 |
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