| programmerjake | markos (and others): i posted a proposal for defining ABI size/align for SVP64 vector types: https://bugs.libre-soc.org/show_bug.cgi?id=1005#c5 | 01:00 |
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| Ritish | toshywoshy: How do I download it x.x | 17:02 |
| Ritish | the meeting ended too fast ig | 17:04 |
| Ritish | Do you want these to be mailed, or should they rather be on that website itself, hmmm | 17:04 |
| Ritish | me shall sleep, will look at it tomorrow | 17:08 |
| Ritish | zzzz | 17:08 |
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| octavius | lkcl, does the ls2 soc l0cache consist of 8 entries of 128-bit wide, as well as having one l0 for odd addresses, and one for even)? | 17:38 |
| octavius | Also, how big is l1 cache, and is it also split into instr/data caches? | 17:39 |
| octavius | This was not clear in the memory and cache page of the wiki | 17:39 |
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| lkcl | octavius: there is no l0 cache. that's for a future (massive) design. | 21:28 |
| lkcl | the l1 cache is defined by compile-time config options. you can look them up. i've forgotten where they are so it's just as much time for you to look them up as it is for me. | 21:29 |
| lkcl | (but i know they are there, which is the important thing) | 21:29 |
| programmerjake | lkcl: https://lists.gnu.org/archive/html/directory-discuss/2022-09/msg00000.html | 21:51 |
| programmerjake | yeah, so they didn't actually finish changing their trademark policy afaict | 21:52 |
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