Thursday, 2023-03-16

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toshywoshymarkos: yes that should work according to the specs07:47
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markostoshywoshy, I see that power8 can use 1600Mhz DDR3 as well10:17
toshywoshyWell, any RAM that is compliant with the full JEDEC spec will drop down, to the CPU or memory controller Mhz10:18
toshywoshythe POWER8 cpu and Centaur RAM controller on those machines runs on 1333Mhz, but you can put faster memoery in there, it just won't work at those speeds10:18
markosI'm asking because I found a "POWER8 Memory Buffer" which states the "Operational maximum frequency targets" as DDR3 - 1600Mbps10:23
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markosand it also seems to support 16GB DIMMs which is great as I found a cheaper 128GB 8x16GB DDR3 12800R listing on ebay10:24
markos the document I mentioned10:24
markosalso, do you happen to know what kind of rack rails these systems take? I could not find any such info on either tyan's site or the ebay seller10:35
markosthe good thing is that all docs are still available on tyan's site10:35
toshywoshythe buffer document you link to is a general one, in general the POWER8 and POWER9 machines have 2 types of memory buffers, the Centaur buffer, can be DIMM RAM based and the CDIMM RAM ones, in one the buffer is common for all DIMMs and in the other each CDIMM has it's own Centaur buffer10:42
toshywoshythe Tyan one is a general Centaur Buffer, so it will fall back to the lowest speed, mostly being the CPU10:43
toshywoshyin the POWER8 systems there are 3 types of CPU. an SCM, and SCM buffered, and a DCM bufferd, each type had 2 iterations, sometimes referred to as POWER8 and POWER8+10:45
markosah right10:46
toshywoshyTyan only produced systems with the very eary POWER8 CPU with a common Centaur buffer, so the CPU will be the slowest comoponent and the front side bus will drop down to that speed, which if I remember well is the 1333Mhz10:48
toshywoshyAs for the rails, I do not remember which rails, but I do rmember that they were fixed rail kits, and quite difficult to take in and out of the rack, I will see if I can find some information on that10:51
markoseg will this ram work? even at lower speed:
markosit's 128gb at a lower price than the other at 64gb10:55
toshywoshyyes, these should work11:00
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markosgot 2x 128GB for 68eur, that's a good deal -if they work at all :)11:43
markossorry, 68eur each11:43
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markoslkcl, can setvl take a dynamic VL?16:36
markosjust saw a particular piece of code that copies only up to certain bytes, but this is runtime known only16:37
markosin particular up to min(64, N) bytes16:39
markosnote, I'm not asking for something like fail-first16:46
markosie on a condition if it finds a null-byte or something siilar16:47
markosbut this is necessary if I need to process eg. 64 bytes at a time in an algorithm16:47
markosin order to handle the remaining bytes16:47
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ghostmansd[m]programmerjake, that's yet another example of "overreacting", eh?16:51
programmerjakeidk, they may have just done that on their own volition. i haven't researched it beyond reading the phoronix article16:56
programmerjakemaybe they knew that company was sanctioned and didn't understand what restrictions that meant were legally required so refused out of caution?16:58
programmerjakeit's also totally possible they used that as an excuse and just don't like russia, idk16:59
programmerjakeor maybe that someone from their govt. told them they didn't like them accepting patches17:00
markosoh wait, it already can do that (set VL dynamically, that is) from a register! exactly what I want17:15
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lkclmarkos, yes. when RA!=0 then the equation is: VL = RT = MIN(MAXVL, RA)19:46
lkclyou're talking literally and precisely about the *original* Cray-I ISA from which setvl originates19:47
lkclanything in addition to that (CTR-setting Mode, VFirst Mode) is new19:47
lkcli believe the Cray Y-MP-1 technical reference manual is available online, it has the complete ISA listing19:49
lkclyou may find these fascinating
lkclin particular
lkcl0020xk - "Transmit register Ak to VL"19:52
lkclmarkos, just remember to set MAXVL to the required maximum allocation of elements20:05
lkclthat's what makes the difference between Cray, RVV, NEC SX-Aurora and other Cray-like Variable-length Vector ISAs: MAXVL is the number of *elements* not a *hardware*-architecturally-defined hard-coded constant20:06
markosyup, already found it, checked the pseudocode again :)20:44
markosalmost done20:45
markoslkcl, is sv.add/w=32 *x, *x, *j enough if I want to have additions happen in 32-bit chunks of a bunch of registers or do I have to do anything extra?22:03
markosnever mind22:09
lkclyep, all packed.22:57
lkclno zeroing, no gaps22:57
lkcl*including* if VL is an odd number22:57
lkclso the last element will *not* wipe out the top-half of the (actual, underlying, 64-bit) last GPR22:58
lkclits contents *remain* intact.  because what actually happened in the hardware was: the 4 byte-write-enable lines to that GPR for the *bottom* half are activated, whilst the 4 for the *top* half are NOT22:59
markosalmost there23:02
markosso, I have the basic logic in encrypt_bytes all done23:02
markosit produces exactly the same cipher as the C code when *no quarterround* is called in both cases23:03
markosbut when I enable the quarterrounds -which I have moved to a macro23:03
markosit fails23:03
markosI think I might be clobbering some register somewhere23:03
markosneed to investigate23:03
markosbut it's good progress23:03
markosthe quarterround snippet is exactly the same as the smaller function and it works there23:04
markosanyway, I'm beat I'll continue tomorrow, I'll let you know :)23:06

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