Wednesday, 2023-05-10

programmerjakesinpi is how the user can work around fp not being able to represent large multiples of pi00:00
programmerjaketo some extent, anyway00:00
programmerjakee.g you still can't compute sinpi(2^1000+0.5) since the input will be rounded to 2^1000 before sinpi ever sees it00:02
programmerjakebut sinpi still correctly computes sinpi(2^1000) = 000:03
programmerjakelkcl: what do you think of adding support for XER.SO but not changing any existing uses of XER[SO]...that way we can write XER.SO if we like in new instructions00:04
programmerjakei was also thinking the parser could translate XER[SO] to XER.SO internally00:05
programmerjakeso the markdown stays XER[SO] but behaves like XER.SO and we don't need a SO constant00:06
programmerjakethe translation would probably be for indexing any all-caps variable with any single all-caps compound expressions...we'd have to watch out for things like V[XLEN] tho00:07
lkclas long as the original syntax may be auto-generated i don't mind00:08
programmerjakek, sounds good!00:08
lkclplease please remember at all times that this is literally the specification for the Power ISA.  all and any changes require a massive (implicit) cost to propose the corresponding changes to the ISA WG00:09
programmerjakeone other thing i thought of: adding an explicit syntax that translates to subscript, rather than using v[] which conflicts with when the pdf uses [] literally00:18
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programmerjakeI changed ISACallerHelper to take an initial required FPSCR value, but I left the two properties in because that's what XLEN does presumably to handle the case when FPSCR is changed in self.namespace06:13
programmerjakelkcl, as part of implementing all the bfp_* functions needed by fcvt*, I need to add a class that's unlike SelectableInt in that it has an effectively infinite size (bigger than 256-bits needed in some cases), it is not an integer, and it is MSB0, and sliceable, so I'm creating a new class for that.06:16
programmerjakethis is for significand in the floating-point working format06:17
programmerjakealso the bfp_* class ^ needs an infinite number of trailing zeros or an infinite number of trailing ones ... you can think of it as a bit-reversed python int06:23
programmerjakeactually, I think I'll implement it as a bit-reversed python int...06:24
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lkclprogrammerjake, no please don't proceed with things like that without discussing it!12:00
lkclthere already exists a mechanism for "unlimited length SelectableInt"12:00
lkclsearch for "256" in SelectableInt and simply increase that number. better: put it as a constant rather than a magic-number12:01
lkcli'm sorting that out now12:05
lkclall that's needed to have an infinite number of trailing 1s is to use EXTS.  job done.12:07
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lkcli'm increasing it to 1024 and adding a new const EFFECTIVELY_UNLIMITED12:28
lkclEXTS was designed *over two years ago* to always return effectively unlimited numbers, and all operations call check_extsign to perform lazy-sign-extension to the *actual* bit-length once it is known12:30
lkclthere is *no need* to add entirely new classes, please remember to consult and ask *before* going ahead with radical decisions that take up a lot of your valuable time12:30
lkclok unit tests passed after extending to 102412:31
lkclit would be much better to have that at the absolute bare-minimum size that cannot be confused with anything (257, 258) as it places a large execution burden on CPUs12:34
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knarhello, so i have been dwelling in errors while installing cavatools.14:20
knarhere is what i did.14:20
knar$git clone
knarthen cloned all the 4 repos into a directory riscv-tools.14:20
knarcheckedout risv-opcodes to relavant commit.14:20
knarcavatools needed riscv-isa-sim to be built so on to that repo.14:20
knarset RISCV env to the riscv-tools directory i just created.14:20
knar$ mkdir build14:20
knar$ cd build14:20
knar$ ../configure --prefix=$RISCV14:20
knarthen i get this error14:20
knarig im not able to make out what the env variables should be set to.14:21
knarany help would be much appreciated14:21
knaralso I found out riscv-opcodes have changed their filenames of the opcodes so had to go back to a commit in 2021 to get the required format needed for cavatools14:22
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lkclknar, in all honesty none of us here have compiled it, and yes cavatools was developed around 2021. for the time-being you are on your own, it would be very helpful if you could make sure to take notes and put them in the wiki and/or bugtracker15:19
lkclif you need a bugzilla account and do not already have one please let me know if you are happy with the Charter then PM me an email address and i will create an account for you15:20
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vaino[m]Hello everyone, I'm a student from Finland, very interested in hardware. I'm hoping to deepen my knowledge following the developments here and maybe contribute once I get the hang of this stuff. Looking forward to interacting with you all. :)15:40
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lkclvaino[m], cool! welcome!16:26
lkclwe have people from all over the world - six timezones i think (!)16:27
lkclyou know we have NLnet grants so you can not just "help" you can actually get paid for it16:30
lkclwhat course are you doing at university? (i assume you're at uni?)16:31
vaino[m]I've read about the grants, I think that's wonderful :D I just finished high school actually, and I've applied for courses centred around electrical engineering and what they call "digital systems and design"16:43
vaino[m]I don't have much experience in all this hardware stuff like HDLs, my knowledge ends at assembly language and some basic circuitry :P16:45
lkcloh nice16:45
lkclwell as we are all software engineers we treat HDL as "yet another programming language"16:46
lkcland if you've done circuit design esp. logic gates then that's basically all that HDL is: "AWayInAProgrammingLanguageToExpressLogicGates"16:47
lkcli didn't have any experience in HDL four years ago at all16:47
vaino[m]I see, that's neat, it's almost like all these mathematical languages in a sense16:51
vaino[m]for nmigen, is there a suggested simulator for testing code? is there one used preferentially16:52
vaino[m]if that's how it works :P16:52
vaino[m]Ah I see seems like nmigen has its own simulator16:53
lkclnmigen contains its own si... yes :)16:58
lkclthere's a tutorial page / find-other-stuff page
lkclsome of those you now have to use to find them (sigh)16:59
lkclthe devscripts should get you up-and-running very quickly17:00
lkclfollow the instructions precisely and exactly and to the letter!17:00
lkcldon't whatever you do try to get creative or go "i'm using OS distro X, i don't have to listen to that advice"17:01
lkclif you do that, i look forward to your reaction in 3 weeks time :)17:01
lkclbut if you follow the instructions and it takes longer than 3 hours to get everything running, come back to us immediately ok?17:02
lkclyou've a system with a minimum of 16 GB RAM?17:02
lkcl8 GB will be painful but just about ok17:03
vaino[m]yes, i do17:03
lkclok awesome17:03
vaino[m]thank you for the resources by the way, I appreciate it :)17:03
lkclno problem :)17:04
lkclbtw if you stick around and want to consistently do useful stuff we can justify getting you an FPGA board17:04
vaino[m]sounds great, I'll see what I can do, I'll have a lot of free time to study this stuff very soon :)17:06
lkclawesome. btw we have tuesday meetings online at 19:00 UTC, usually goes on randomly for 1hr30m all sorts of topics (it's an open discussion), if you're interested i can PM you the URL?17:08
lkcl(or email me and i can add you to the google calendar-invite)17:09
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vaino[m]Sure, I'll be available by then, could you PM me the link? Thanks17:28
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ghostmansd[pc]markos, please avoid committing debug printouts :-)18:16
markos_usually I don't commit them, but must have missed one, where was that? :)18:17
ghostmansd[pc]if needed, please use util.log18:17
ghostmansd[pc] :-)18:17
ghostmansd[pc]I'll revert these if they're not needed anymore, OK?18:17
markos_ah yes, indeed, apologies :)18:18
markos_yes, please go ahead and remove them18:18
ghostmansd[pc]done, thanks :-)18:20
ghostmansd[pc]BTW, I totally understand why you added them there18:20
ghostmansd[pc]that's one of the most gory places18:20
ghostmansd[pc]probably the most gory except of registers remapping18:20
ghostmansd[pc]that one still beats anything else by factor of magnitude18:21
markos_trying to make out what's going on in there was hard :)18:21
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ghostmansdno surprise, now imagine how hard was actually writing this :-D18:21
ghostmansdany ideas on simplifying this crap are always welcome :-)18:22
markos_I would really love to have a UI for all this info, something that parses all those logs and presents them in a readable fashion, like some CPU simulators18:22
markos_well, not simplifying18:22
markos_but grouping in a more presentable way18:22
markos_doesn't have to be a GUI18:22
ghostmansdyou mean, about the whole information we can get from these shiny CSVs et al.?18:22
markos_even curses style interface18:22
markos_in the past I've used some GUI CPU simulator from Freescale18:23
markos_I think it was called, simG4? simG5?18:23
markos_can't remember the name18:23
ghostmansdlike, "this insn has X operands and these bits are go like this"18:23
ghostmansdor do you mean logging?18:23
markos_it presented a full simulation of the CPU, the currently executed program, separate places with real time info for the registers, current states, etc18:24
ghostmansd(what we have is not a logging, to be honest)18:24
markos_that was in a UI18:24
markos_window based, but it ran on Linux18:24
ghostmansdaaaah I get what you mean18:24
markos_you could literally step into each instruction, like a debugger but much more low level18:24
ghostmansdyeah guessing this all from logs is hard18:24
markos_it showed info about "bubbles" in the pipeline, how many cycles each instruction lost waiting for the next instruction to be decoded, or from data to be fetched from memory/L1/L2 cache, etc18:25
markos_it was really powerful18:25
markos_and allowed for some really careful hand tuning of the assembly code to avoid stalls, and make sure that every unit would not be left un(der)utilized18:26
markos_though this was tuned to specific hardware models of the CPU, but you could select from a list18:26
markos_really really powerful18:26
markos_we could have something similar, I mean most of the info is there, we could just export it in a certain way (JSON?), and provide a dumb UI that just presents the info in a certain way18:27
markos_realtime view of the registers/schedulers/memory/etc18:27
markos_I suck at UI stuff so someone else has to do it though :-P18:28
markos_lkcl, what do you think?18:28
markos_we could extend pypowersim to do that, unless cavatools can do that stuff already18:28
ghostmansd+1 for that idea18:29
ghostmansdeven if cavatools has the UI, having an option to export this stuff is a nice option18:30
ghostmansdwe kinda have the basic building blocks in our simulator... I mean, any Python stuff can at least be pickled18:31
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markos_I mean even Z80 has a ton of nice GUI simulators, why can't we :D18:32
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octaviusvaino[m], thanks for your interest!18:34
octaviusCurrently I'm working on a tutorial for Microwatt simulation (a basic scalar subset POWER core, from which Libre-SOC had much inspiration...), and hopefully a video should be available by the end of the week.18:34
octaviusIf you have trouble with nMigen, just post here, I'll try to help when I can.18:34
octavius(also when you see the dev list emails, my name is Andrey).18:34
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lkclghostmansd, but but i love!18:43
lkclmarkos_, that's what cavatools curses-console does.18:43
lkcland also the plan is to have the model-simulator output a brain-dead-simple markdown output file18:44
lkclwith each "stage" as a column18:44
markos_markdown? for post/offline processing? sounds like a strange format choice, but ok18:45
markos_I would expect something like csv/json and then some processing on those to generate what you want18:46
lkcljust a table.  | insn | stage1 | stage2 | stage3 |...18:46
lkclcsv would work too18:46
markos_well, if markdown does the job, why not18:46
markos_what would the cell in each stage be?18:47
lkclin *this* model which is the *first* model18:47
lkclstage4-and-above is execute18:48
markos_in another simulator, I've seen a vertical table, with cycles as the left column, and each unit (ALU/FPU/Vector/Load/Store) in its own column,18:48
markos_that shows the utilization of each unit, per cycle18:49
lkclthat doesn't allow for showing pipeline progression18:49
markos_ofc that's hardware specific, some cpus might have more than one units of each18:49
markos_no indeed18:49
lkclwhich will have to be the next model and/or have multiple entries per cell18:50
markos_well, at least ideas are not something we're going to run out of :)18:51
programmerjakethere is:
programmerjakeyou'll need to enable javascript and webassembly18:53
vaino[m]octavius, nice to meet you :) I'd gladly watch that video once it's out.18:54
programmerjake(generally enabled by default in modern browsers)18:54
markos_ah nice! yes, something similar, though imho, it would easier to show cycles vertically18:55
markos_but yes, it's nice, didn't know we had something like that already18:55
programmerjakejust edit the command line to remove --transpose text box18:56
markos_curious, what's using webassembly?18:56
programmerjakeoh, it's written in rust and c++18:57
programmerjakeit simulates a register-renaming OoO superscalar cpu, but it has no decoder and only supports like 5 instructions18:58
programmerjakelkcl told me to quit working on it cuz it's written in rust/c++18:59
markos_ah so it's a separate project? it doesn't use pypowersim output?19:00
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programmerjakeit has a full command line interface, so, e.g. you can give --help to see what commands it supports, iirc you can also compile the code to an x86 or other binary if you like19:01
lkclyes it is - an unfunded one that is so large that it should have had an NLnet Grant application created and approved to fund it *before* even starting the work19:01
markos_yeah, I think I remember, I think it would be worth to have something that parses the output of the existing pypowersim and visualize it, but this is an entirely new project19:01
markos_and we would have to maintain both -plus cavatools- with any change in the ISA19:01
programmerjakeyes, it has a hardcoded instruction trace input
lkclthe idea is to add about 5 lines of code to pypowersim to get it to output the current instruction into a log file.19:02
lkcl(plus the PC, plus the address of load/store if there is one)19:03
markos_the more data the better, as long as we can process and visualize it, log files as they are right now are pretty much unreadable unless you're looking for a very specific piece of information19:03
lkclactual contents of memory and actual contents of regfiles are paradoxically utterly irrelevant for the model19:03
lkclwhich is why a total rewrite (from scratch) of yet another simulator should never have had time spent on it19:03
lkclto get an actual useful model you *need* the sequence of instructions for analysis19:04
markos_they are irrelevant for the model, but are very relevant if you're using the simulator to debug actual code19:04
markos_like I was doing for example19:04
lkcland we already have such a tool: called "pypowersim"19:04
lkclyes. this is very specific, it is needed for making commercial justification presentations19:04
lkcla secondary (just as important) goal is to spot blackspots (stalls)19:05
programmerjakethe rust/c++ simulator i wrote behaves very much like the in-order python pipeline simulator you're currently writing, it simulates register dependencies, not actual data computation19:05
programmerjakeexcept that the in-order cpu simulator is much less like modern high-end cpus and what we want libre-soc's cpu to finally end up as19:07
programmerjakeso the program i wrote is right now more representative of our final cpu19:08
programmerjakesince in-order cpus can't do OoO superscalar19:08
programmerjakeand our final cpu will be OoO superscalar (but using a different algorithm)19:10
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lkclokaay two new unit tests for data-dependent fail-first, one vli one without19:33
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lkclstore is trickier: for VLI=0 it requires the workaround to explicitly test the data to be stored *before* even *attempting* the store19:34
lkclthe alternative - to shadow-hold the memory-write - is kinda odd19:34
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ghostmansd[m]lkcl, thank you for your kind words on insndb!19:45
ghostmansd[m]I'm refactoring some of its chunks to make it be better usable for and pysvp64asm19:46
ghostmansd[m]But not much, mostly decoupling common bits19:46
lkclfunnily enough the only thing needed is to identify the registers19:47
lkcland that's done through ISACaller... okok now called ISAPages (see decoder/isa/ after re-running pywriter)19:47
lkcl    fixedarith_instrs = {}19:48
lkcl    fixedarith_instrs['addi'] = instruction_info(func=op_addi,19:48
lkcl                read_regs=OrderedSet(['RA']),19:48
lkcl                uninit_regs=OrderedSet(), write_regs=OrderedSet(['RT']),19:48
lkclthat's good enough for now19:48
lkclno need to use insndb at all for this19:49
lkclwhen SVP64 is added that's a different matter19:49
lkclbuuut.... even there, it *may* be possible to get away with not needing it by outputting to the log file the reg nums *after* parsing19:49
ghostmansd[m]Don't we have to check GPR/FPR/CR?19:50
ghostmansd[m]And, also, immediates19:50
lkclthat can be done by name (as it is somewhere inside... errr... i forget where)19:50
lkcl"if name in ['RA', 'RB'...] -> GPR19:50
lkcl"if name.startswith("R") -> GPR19:51
lkclit's *that* level of basic19:51
lkclimmediates can be utterly ignored19:51
lkclthey are irrelevant as far as register hazard checking is concerned19:51
lkclwhich is the first top-priority task for the model19:52
lkclyou can see, i created a set() inside inordermodel.py19:52
lkcland already put in the code to check "are we waiting for another ALU to write to this reg? if so stall"19:53
ghostmansd[m]I'll check in about an hour, right now putting a daughter to bed :-)19:53
lkclok :)19:53
ghostmansd[m]If we have stuff like "add 1,2,3" as input, how do we get if name starts with R?19:55
ghostmansd[m]If and only if we have say "add r1,r2,r3", we can know this19:56
ghostmansd[m]But our disassembly does not follow this convention (not unless we ask it politely)19:57
programmerjakei think lkcl means the field name not the asm code19:57
ghostmansd[m]I understand19:58
ghostmansd[m]But, again: without relying on CSVs, we do not know field name19:59
programmerjakee.g. where isacaller passes input registers into the compiled pseudocode function19:59
lkclghostmansd[m], same as it is done in ISACaller. strip the name, use that as the lookup19:59
lkclsearch "self.instrs" in ISACaller19:59
ghostmansd[m]Ok I'll check it, thanks!19:59
lkclthe awkward bit is the duplication of all the nonsense of "." in the name etc. etc.20:00
lkclyou will see a hell of a lot of bullshit in ISACaller, which should be put into a common function20:01
ghostmansd[m]Anyway, I'll complete some stuff in insndb, since I already started it and it's useful per se. Basically providing assemble/disassemble methods to be reused, assemble is the same it's done in pysvp64asm and disassemble is... You get the idea.20:01
programmerjakelike here:;a=blob;f=src/openpower/decoder/isa/;h=0807e47a42e17359dbabf7d871acdfde9fef516f;hb=HEAD#l205920:01
lkclyehyeh. hurrah20:01
ghostmansd[m]I think we'll need these later20:01
programmerjakelkcl: imho we still need the Fraction-based class since it doesn't behave like SelectableInt20:03
ghostmansd[m]Still not entirely obvious how create_args works20:03
ghostmansd[m]What are the inputs and the outputs20:04
ghostmansd[m]I see it outputs list of names20:04
ghostmansd[m]Are these RA, FRT, et al.?20:04
programmerjakeghostmansd: yes, they match the function arguments and return values in the compiled pseudocode20:05
programmerjakethose names come from info.read_regs and info.uninit_regs20:06
ghostmansd[m]OK, assuming I have an input "add 1,2,3". How do I get an idea where is RT and RA and whatever else unless I have parsed CSV or unless there was another module which parsed CSV told me this info?20:08
ghostmansd[m]I should either have an additional input which tells me operand names, or I should parse the instruction on my own.20:09
ghostmansd[m]Am I missing something, guys?20:09
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programmerjakelkcl: the Fraction-based class has unlimited range in both directions -- toward more significant bits and toward less significant bits, SelectableInt stops at bit 0. also mul/div behave differently. those are all needed for bfp_* functions20:10
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programmerjakeghostmansd, i think the idea is to add code to isacaller that produces an instruction trace, you can just plain include input_names in the trace to use later20:12
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programmerjakejust include whatever info you need, maybe `info` itself20:13
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ghostmansdF*ck hexchat is probably the dumbest IRC client I've ever seen20:16
ghostmansdAlways disconnecting, always keeping the nickname occupied20:16
ghostmansdprogrammerjake, everything above still counts as an additional input :-)20:16
ghostmansdOK, so, the trace MUST be generated by something like ISACaller, right?20:17
ghostmansdand this trace can be in any form I find appropriate20:17
programmerjakeso, you don't actually need the list of which of RA/RB/etc. it reads but instead which physical registers the instruction reads/writes since those are what are actually used for dependency tracking20:17
programmerjakeprobably a list, yeah20:18
programmerjakethough something that can go in a file is nice too20:18
ghostmansdYeah I've been thinking about a file20:19
ghostmansdAnd basically it boils down to "now something reads GP register numbered 0"20:19
programmerjakemaybe add tracing to ISACaller.get_input? that's where reg reads actually occur iirc so it has the right reg nums20:19
ghostmansdand "now something writes GPR numbered 0 and reads from GPRs numbered 6 and 7"20:19
ghostmansdLike this?20:20
programmerjakethough you'll probably also want the asm string so users can see what's currently running20:21
ghostmansdHm... Hm hm hm...20:21
ghostmansdOK I think I understand20:21
programmerjakeactually, it might be better to trace directly in the GPR class, since that's not the only place gprs are read/written20:22
ghostmansdA dumb question: how do I run ISACaller?20:22
programmerjakesame thing with FPR and others20:23
ghostmansdSay I have some instruction, e.g. "add 1,2,3"20:23
ghostmansdAnd I want to add some code to ISACaller which produces the trace.20:23
ghostmansdThen I want to feed the insn to ISACaller.20:23
ghostmansdSorry, never ever run it other than indirectly.20:24
programmerjakesimplest way: invoke just like all the unit tests do -- see;a=blob;f=src/openpower/decoder/isa/;h=7df7a457558a5b837be83dc2d0de436ab661936e;hb=HEAD20:24
programmerjakesince that requires zero extra thought :)20:24
programmerjakethough you could look through the unit tests, some invoke isacaller more directly20:25
ghostmansd> since that requires zero extra thought :)20:25
ghostmansdI admire your style sir!20:26
ghostmansdPerfectly fits my needs20:26
ghostmansdAh yeah I recall some tests instantiated ISACaller20:26
ghostmansdProbably even one written by me...20:26
ghostmansdToo long ago to remember20:26
programmerjakeone that calls it more directly:;a=blob;f=src/openpower/decoder/isa/;h=0e3796b47a47a6aa80a8cb718a5684a84992a533;hb=HEAD20:27
programmerjakerun_tst, not ISACallerHelper shenanigans20:28
programmerjakerun_tst defined here (after looking through multiple layers of importing imports...sigh);a=blob;f=src/openpower/decoder/isa/;h=b84354cc099cfba908629b9c17b903990fc79388;hb=HEAD20:30
ghostmansdThanks programmerjake!20:33
ghostmansdI think that was a great start20:33
programmerjakeyw! hopefully that's what luke intended...20:34
lkclprogrammerjake, ah a class that is *external* and *non-intrusive* to SelectableInt - i.e. requires absolute flat-out zero modification of SelectableInt - as long as it is not thousands of lines of code - i am fine with20:36
lkclit's when you write code that is five times longer than anything anyone else would ever write, placing anyone else in the team under a huge maintenance burden, that's when it's a problem20:37
lkclghostmansd, yes you did the.... ah.... bcd instructions i think? or it was around that time20:37
programmerjakeyeah, all it does is hand out SelectableInt when sliced, otherwise doesn't interact with SelectableInt iirc20:37
lkclthen i don't have a problem with it, especially if it just overrides one single function, that's perfect20:38
lkclghostmansd, here's one20:39
programmerjakecan you review the new branch?;a=shortlog;h=refs/heads/support-fields20:39
lkcl-    def __init__(self, XLEN):20:39
lkcl+    def __init__(self, XLEN, FPSCR):20:39
lkclah strictly speaking these need to go20:40
lkcl-    def FRSP(FRB, FPSCR):20:40
lkcl+    def FRSP(FRB):20:40
programmerjakewhat do you mean?20:41
lkclthe concept of return and of function-definitions is not part of the Power ISA pseudocode specification20:41
lkclthe only reason it works is because i had based the parser on by David Beazley20:42
lkcland had not removed function-header and return-result from the BNF!20:42
programmerjakeit totally is...see bfp_ABSOLUTE() for a short example20:43
lkclit's a pain-in-the-ass to remove but also i am wavering as to whether it should stay as it makes the pseudocode much more readable20:43
lkclyou did a rewrite about a year ago of the FRSP pseudocode20:43
lkclputting in function headers and splitting it from its string-based if/elif form into functions20:44
programmerjakewell, do you want to add goto support? sounds like fun figuring out to implement that in python...20:44
lkclwhich as i mentioned yesterday has the implication of the INTENTION to propose the exact same modification *to the Power ISA*20:44
lkclthat's a good enough justification that i can present to the OPF ISA WG20:45
lkcl(that and readability)20:45
programmerjakethose were gotos, not string-based if/elif iirc20:45
lkcli'm not keen on passing FPSCR as a parameter20:46
programmerjakehence why it's not anymore20:46
lkclok :)20:46
programmerjakeyou read the diff backwards20:47
lkclaw doh20:47
programmerjakeso, good to merge to master?20:47
lkclgis a minute - wading through a 7/10 headache20:48
programmerjakek, hope you feel better...20:48
* lkcl just doing a global diff20:50
programmerjakethat'd be a mess...i split it apart into understandable diffs20:52
lkclyeah all good20:52
lkcli get a quick overview of everything. it works20:52
lkclyep all good, go for it20:52
programmerjakeparticularly the moving functions around in the parser and then modifying them20:52
programmerjakek :)20:53
lkcli'm not concerned. if it works it works20:53
programmerjakerunning tests...20:56
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programmerjakemore broken tests, luke, but matches master so i'm pushing21:02
programmerjakeFAILED src/openpower/decoder/isa/
programmerjakeFAILED src/openpower/decoder/isa/
programmerjakeFAILED src/openpower/decoder/isa/
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lkclah that's new, i know why, too21:19
lkcli stopped regfile writing from occurring on dd-ffirst for LD21:20
lkclghostmansd[m], octavius, i'm an idiot: no need to read insndb at all21:51
lkclhave ISACaller write out the instruction *and* the registers used21:51
lkclinsn 1,2,3 # GPR:RT=1 GPR:RA=2 GPR:RB=321:51
lkcland this has the advantage that when writing to CR0/CR1 this can be explicit and easy too21:52
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ghostmansd[m]Yeah that's what programmerjake basically suggested above21:55
ghostmansd[m]I'm not sure if we even need to output the whole insn. Even name seems to be needed for debug only.21:55
lkclpretty much22:54
lkcli'll add Rc=1 shortly23:12
programmerjakelkcl: please pass a path to use in from TestRunnerBase, using nmutil.get_test_path, the temp -ath you chose conflicts between all parallel invocations of ISACaller (or actually all invocations between reboots since you open it in append mode)23:26
programmerjakethat also allows a different path per case_* fn23:28

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