Wednesday, 2023-05-24

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lkclprogrammerjake, FP trap looks great - do remember to pass in ExpectedState for SRR0 (PC at the trap point) and SRR1 (includes the PR.FP flag bit set)10:35
lkclthe Test API ignores SPRs that aren't actually passed in for testing10:35
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programmerjakei looked but didn't see srr0/1 and msr in expectedstate10:49
programmerjakehttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/fmv_fcvt/fmv_fcvt.py;h=e4803f7549165c339c8db58c3dfbcbc8a4e78c13;hb=bd6445153bf9ad2d571fcfc84533eb5709769226#l13910:50
programmerjakeif expectedstate did check srr0/1 and msr, it would have failed the unit test and i would have noticed10:51
lkclyes you have to add them. MSR i think isn't actually compared (whoops)11:14
lkclbut SPRs are11:14
lkclbut *only* if you pass some in.11:14
lkcllet me check...11:14
lkclnope.11:15
lkcltotal lie :)11:15
lkclbeen such a while - i think it's something that was planned rather than actioned11:16
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programmerjakeadded a todo11:54
programmerjaketo https://bugs.libre-soc.org/show_bug.cgi?id=1072#c011:54
programmerjakettyl, 4am here11:55
lkclk cool. good to get sorted.11:56
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