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lkcl | programmerjake, FP trap looks great - do remember to pass in ExpectedState for SRR0 (PC at the trap point) and SRR1 (includes the PR.FP flag bit set) | 10:35 |
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lkcl | the Test API ignores SPRs that aren't actually passed in for testing | 10:35 |
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programmerjake | i looked but didn't see srr0/1 and msr in expectedstate | 10:49 |
programmerjake | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/fmv_fcvt/fmv_fcvt.py;h=e4803f7549165c339c8db58c3dfbcbc8a4e78c13;hb=bd6445153bf9ad2d571fcfc84533eb5709769226#l139 | 10:50 |
programmerjake | if expectedstate did check srr0/1 and msr, it would have failed the unit test and i would have noticed | 10:51 |
lkcl | yes you have to add them. MSR i think isn't actually compared (whoops) | 11:14 |
lkcl | but SPRs are | 11:14 |
lkcl | but *only* if you pass some in. | 11:14 |
lkcl | let me check... | 11:14 |
lkcl | nope. | 11:15 |
lkcl | total lie :) | 11:15 |
lkcl | been such a while - i think it's something that was planned rather than actioned | 11:16 |
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programmerjake | added a todo | 11:54 |
programmerjake | to https://bugs.libre-soc.org/show_bug.cgi?id=1072#c0 | 11:54 |
programmerjake | ttyl, 4am here | 11:55 |
lkcl | k cool. good to get sorted. | 11:56 |
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