Wednesday, 2024-01-03

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ghostmansd[m]Hi folks, a quick (hopefully) question on the difference between (RA) and RA for pseudocode. Does (RA) means "dereference an address contained in the register"?10:53
openpowerbot[irc] <programmerjake> it means read the register numbered RA. RA by itself, when used as an input, means get the register number instead of the register's contents11:09
openpowerbot[irc] <programmerjake> see PowerISA v3.1B book I section 1.3.211:12
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ghostmansd[m]Thanks programmerjake!13:56
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ghostmansd[m]Yet another question on registers. Sometimes we see _RA, not RA. I vaguely recall these are the same, and we even likely had a task to unify them. Is it correct and I should treat _RA as RA?17:25
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ghostmansd[m]Example: simplev.mdwn, setvl pseudocode17:30
sadoonaltHi guys17:33
sadoonaltI don't wanna deal with finding a good IRC client so this will do for now17:33
sadoonaltBetter focus my time on finishing up and preparing for FOSDEM :D17:33
sadoonaltregistered this account in case I have to use it for longer17:37
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openpowerbot[irc] <programmerjake> since python can only have one variable named RA and that's already used by the simulator to store RA's value (not register number), RA_ is used to store the register number when needed. yes, this doesn't match the PowerISA spec.20:32
sadoonaltUsing DSRD, is this the expected behavior? a = 0x0123456789ABCDEF b = 0xFEDCBA9876543210 ; test11, test12 = DSRD(a,b,44)20:45
sadoonalttest11 = 56789abcdef00000 test12 = fedcba987650123420:45
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openpowerbot[irc] <programmerjake> yes, that's correct. whoever wrote the DSRD function by extracting it from got the return values backward from what I would have expected: it returns (RS, RT), I would have expected (RT, RS)20:54
openpowerbot[irc] <programmerjake> dsrd shifts the first input and ORs-in the second input in the bits where the first input was shifted out of20:55
openpowerbot[irc] <programmerjake> actually, it shifts RA by RB and ors in RC20:57
openpowerbot[irc] <programmerjake> so, whoever wrote that function also has the function arguments in an unexpected order of RA, RC, RB20:58
sadoonaltSo it should be test11 = fedcba9876501234 and test12 = 56789abcdef00000 ?21:00
openpowerbot[irc] <programmerjake> the idea is that when RC and RS are the same register you can do `sv.dsrd/mrr *dest, *src, shift, temp` and it will do a bigint right shift by `shift`21:00
openpowerbot[irc] <programmerjake> i would have expected that, but due to the weird return value order the values you got are correct21:01
sadoonaltOk so I've got this big value split into two registers t0 = 0x0e289fe15c71a31c t1 = 0x5030a22122b44f6521:04
sadoonaltI basically need to split this into three registers, 44,44, and 42 bits21:05
sadoonalth0 = fe15c71a31c (t0 with first 20 bits removed)21:05
openpowerbot[irc] <programmerjake> basically dsrd returns a 128-bit value with the high half in RT and the low half in RS21:05
sadoonaltt0 with first 24 bits removed****21:06
sadoonaltUgh I'm stumbling over myself21:07
sadoonaltok, the lower 44 bits of t021:10
sadoonaltthen the lower 24 bits of t1 stitched as low bits with the higher 20 bits of t021:11
sadoonaltthen the higher 40 bits of t121:12
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sadoonaltbasically h2h1h0 is t1t0, where each h is 44 bits except h0 40 bits21:16
sadoonaltbasically h2h1h0 is t1t0, where each h is 44 bits except h2*** 40 bits21:16
openpowerbot[irc] <programmerjake> ok, you can use dsrd to extract the middle 64-bits (you'll have to mask to 44 bits afterward), use:... (full message at <>)21:17
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sadoonaltHmm Luke seemed to suggest it would be only 2 DSRD calls, I see one in your code with other srd's21:18
openpowerbot[irc] <programmerjake> reposting since matrix linkified my too-long message21:19
openpowerbot[irc] <programmerjake> ok, you can use dsrd to extract the middle 64-bits (you'll have to mask to 44 bits afterward), use:21:20
openpowerbot[irc] <programmerjake> srdi outh, t0, 64-4421:20
openpowerbot[irc] <programmerjake> li temp2, 88-6421:20
sadoonaltno worries, clicked the link21:20
openpowerbot[irc] <programmerjake> srd temp, t0, temp221:20
openpowerbot[irc] <programmerjake> dsrd outm, t1, temp2, temp21:20
openpowerbot[irc] <programmerjake> clrldi outm, outm, 64-4421:20
openpowerbot[irc] <programmerjake> srdi outl, temp, (64 - 40)21:20
openpowerbot[irc] <programmerjake> yeah, but luke doesn't like that since he wants everything to be not-linkified for irclog21:21
sadoonaltoh yeah true, logs don't pick those up21:21
sadoonaltanyways I'll try that tomorrow, past midnight here. Thanks!21:21
openpowerbot[irc] <programmerjake> dsrd works great when you have a list of full 64-bit words that need to be shifted, it works less well when you're trying to prevent C overflow by stuffing stuff in more variables with less than 64-bits each21:23
sadoonaltIn this case t1t0 are full 64-bit words, we just need to shrink them to 40/44/44 bits21:24
openpowerbot[irc] <programmerjake> preventing C overflow is only necessary in C, imo it would be more efficient to use the bigint instructions and use 64-bits per register, but that means refactoring the algorithm which you understandably want to avoid21:25
openpowerbot[irc] <programmerjake> ^ referring to all the logic after converting to 44-bit words in C21:26
openpowerbot[irc] <programmerjake> this is because the bigint instructions are designed specifically to handle arbitrarily big sequences of 64-bit words and not lose information due to overflow21:27
sadoonaltI see21:27
sadoonaltI can use these instructions is isacaller right?21:28
sadoonaltJust like the other SVP64 stuff21:28
sadoonalt(I've been using the python function to test)21:29
openpowerbot[irc] <programmerjake> yes, though note that the asm i gave you you need to convert from aliases to the base instructions since isacaller doesn't support any aliases (except nop)21:30
sadoonaltnot a problem, thanks again and good night!21:30
openpowerbot[irc] <programmerjake> e.g. srdi a, b, n -> rldicl a, b, 64-n, n21:31
openpowerbot[irc] <programmerjake> gn21:31
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openpowerbot[irc] <programmerjake> oh, one other thing, isacaller can't evaluate expressions like addi temp2, 0 88 - 64, you have to change that to addi temp2, 0, 24 (assuming i did my math right)21:38
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