Sunday, 2022-09-25

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ghostmansdlkcl, what'd be the permutations for dz/sz/zz/snz?11:05
ghostmansdFor the first three, it's simple: if equal, output zz, otherwise output if true11:05
ghostmansdFor sz/snz, it's also simple: if snz, sz should also be set, but output only snz; otherwise output sz if it's true11:06
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ghostmansdWhat'd be the combos for /zz/snz?11:06
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ghostmansdlkcl, what'd be the permutations for dz/sz/zz/snz?11:14
ghostmansdFor dz/sz/zz, it's simple: if equal, output zz, otherwise output those which are true.11:14
ghostmansdFor sz/snz, it's also simple: if snz, sz should also be set, but we only output /snz; otherwise output sz if it's true.11:15
ghostmansdWhat'd be the other combos?11:15
ghostmansdI think that, if snz and dz are set, we should output /snz/zz. Is it correct?11:15
ghostmansdAlso, is /snz/dz permitted? Is it permitted for cases when we only have zz and snz bits?11:17
ghostmansdhttps://libre-soc.org/openpower/sv/cr_ops/12:10
ghostmansd/     SNZ     1 VLI     inv     dz sz     Ffirst 5-bit mode12:11
ghostmansdThere's inv, but no CR. Is it correct? How does one set inv? /inv? What does it affect, then?12:14
ghostmansdCR ops disassembly is ready, except for 5-bit failfirst (this one needs an additional clarification).12:51

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