Load Byte and Zero

SVD-Form

  • lbzbr RT,SVD(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0]*56 || MEM(EA, 1)

Special Registers Altered:

None

Load Byte and Zero with Update

SVD-Form

  • lbzubr RT,SVD(RA),RC

Pseudo-code:

n <- (RC)[58:63]
EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0] * 56 || MEM(EA, 1)
RA <- EA

Special Registers Altered:

None

Load Halfword and Zero

SVD-Form

  • lhzbr RT,SVD(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0] * 48 || MEM(EA, 2)

Special Registers Altered:

None

Load Halfword and Zero with Update

SVD-Form

  • lhzubr RT,SVD(RA),RC

Pseudo-code:

n <- (RC)[58:63]
EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0] * 48 || MEM(EA, 2)
RA <- EA

Special Registers Altered:

None

Load Halfword Algebraic

SVD-Form

  • lhabr RT,SVD(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- EXTS(MEM(EA, 2))

Special Registers Altered:

None

Load Halfword Algebraic with Update

SVD-Form

  • lhaubr RT,SVD(RA),RC

Pseudo-code:

n <- (RC)[58:63]
EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- EXTS(MEM(EA, 2))
RA <- EA

Special Registers Altered:

None

Load Word and Zero

SVD-Form

  • lwzbr RT,SVD(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0] * 32 || MEM(EA, 4)

Special Registers Altered:

None

Load Word and Zero with Update

SVD-Form

  • lwzubr RT,SVD(RA),RC

Pseudo-code:

n <- (RC)[58:63]
EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
RT <- [0]*32 || MEM(EA, 4)
RA <- EA

Special Registers Altered:

None

Load Word Algebraic

SVDS-Form

  • lwabr RT,SVDS(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
RT <- EXTS(MEM(EA, 4))

Special Registers Altered:

None

Load Doubleword

SVDS-Form

  • ldbr RT,SVDS(RA),RC

Pseudo-code:

b <- (RA|0)
n <- (RC)[58:63]
EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
RT <- MEM(EA, 8)

Special Registers Altered:

None

Load Doubleword with Update Indexed

SVDS-Form

  • ldubr RT,SVDS(RA),RC

Pseudo-code:

n <- (RC)[58:63]
EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
RT <- MEM(EA, 8)
RA <- EA

Special Registers Altered:

None